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path: root/llvm/lib/CodeGen/MachineRegisterInfo.cpp
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* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders2019-08-011-6/+6
* [Peephole] Allow folding loads into instructions w/multiple uses (such as tes...Philip Reames2019-06-251-0/+7
* CodeGen: Introduce a class for registersMatt Arsenault2019-06-241-3/+3
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [MachineCSE][GlobalISel] Making sure MachineCSE works mid-GlobalISel (again)Roman Tereshin2018-10-201-33/+22
* Re-commit: [globalisel] Add a combiner helpers for extending loads and use th...Daniel Sanders2018-10-031-0/+10
* Remove trailing spaceFangrui Song2018-07-301-1/+1
* [GlobalISel] NFCI, Getting GlobalISel ~5% fasterRoman Tereshin2018-05-231-10/+4
* IWYU for llvm-config.h in llvm, additions.Nico Weber2018-04-301-0/+1
* Adding optional Name parameter to createVirtualRegister and createGenericVirt...Puyan Lotfi2018-04-031-4/+5
* [MIR] Adding support for Named Virtual Registers in MIR.Puyan Lotfi2018-03-301-1/+2
* GlobalISel: Make MachineCSE runnable in the middle of the GlobalISelJustin Bogner2018-01-181-7/+50
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-1/+1
* [CodeGen] Rename functions PrintReg* to printReg*Francis Visoiu Mistrih2017-11-281-4/+4
* [MachineCSE] Add new callback for is caller preserved or constant physregsTony Jiang2017-11-201-0/+7
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-2/+2
* [MachineRegisterInfo] Avoid having dbg.values affect code generationMikael Holmen2017-11-161-2/+2
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-081-1/+1
* Reverting r315590; it did not include changes for llvm-tblgen, which is causi...Aaron Ballman2017-10-151-1/+1
* [dump] Remove NDEBUG from test to enable dump methods [NFC]Don Hinton2017-10-121-1/+1
* LiveIntervalAnalysis: Fix alias regunit reserved definitionMatthias Braun2017-09-011-0/+18
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
* [MIR] Support Customed Register Mask and CSRsOren Ben Simhon2017-03-191-0/+12
* Fixing typos.Oren Ben Simhon2017-03-161-4/+5
* [CodeGen] Fix -Wreorder warning.Benjamin Kramer2017-03-141-3/+3
* Disable Callee Saved RegistersOren Ben Simhon2017-03-141-2/+34
* [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; ot...Eugene Zelenko2017-02-171-7/+20
* Cleanup dump() functions.Matthias Braun2017-01-281-2/+2
* GlobalISel: allow CodeGen to fallback on VReg type/class issues.Tim Northover2016-11-081-11/+0
* MachineRegisterInfo: Remove unused arg from isConstantPhysReg(); NFCMatthias Braun2016-10-281-2/+1
* Fix warning; NFCMatthias Braun2016-10-111-2/+2
* MIRParser: generic register operands with typesMatthias Braun2016-10-111-1/+2
* MIRParser: Rewrite register info initialization; mostly NFCMatthias Braun2016-10-111-7/+10
* [TargetRegisterInfo, AArch64] Add target hook for isConstantPhysReg().Geoff Berry2016-09-271-1/+5
* GlobalISel: remove "unsized" LLTTim Northover2016-09-151-1/+1
* GlobalISel: disambiguate types when printing MIRTim Northover2016-09-121-2/+0
* GlobalISel: move type information to MachineRegisterInfo.Tim Northover2016-09-091-14/+14
* MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness early, do not print/...Matthias Braun2016-08-241-1/+6
* [GlobalISel] Introduce an instruction selector.Ahmed Bougacha2016-07-271-0/+14
* [GlobalISel] Mark newly-created gvregs as having a bank.Ahmed Bougacha2016-07-191-2/+5
* [IPRA] Properly compute register usage at call sites.Chad Rosier2016-07-111-2/+3
* Replace MachineRegisterInfo::TracksLiveness with a MachineFunctionPropertyDerek Schuff2016-04-111-2/+1
* [MachineRegisterInfo] Track register bank for virtual registers.Quentin Colombet2016-04-071-1/+6
* Replace MachineRegisterInfo::isSSA() with a MachineFunctionPropertyDerek Schuff2016-04-041-2/+2
* [MachineRegisterInfo] Add a method to set the size of a virtual register a po...Quentin Colombet2016-03-071-0/+4
* [MachineRegisterInfo] Get rid of the global-isel ifdefs.Quentin Colombet2016-03-071-6/+3
* [GlobalISel][MachineRegisterInfo] Add a method to create generic vregs.Quentin Colombet2016-02-111-0/+16
* [GlobalISel] Remember the size of generic virtual registersQuentin Colombet2016-02-101-0/+9
* Scheduler / Regalloc: use unique_ptr[] instead of std::vectorFiona Glaser2015-12-021-4/+3
* Refactor: Simplify boolean conditional return statements in lib/CodeGen.Rafael Espindola2015-10-241-5/+2
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