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* [NVPTX] Add query support for read-write images and managed variablesJustin Holewinski2014-04-094-3/+52
| | | | | | This also fixes a bug in the annotation cache where the cache will not be cleared between modules if multiple modules are compiled in the same process. llvm-svn: 205905
* Do not rely on invalid pthread API use in thread testEd Maste2014-04-092-24/+22
| | | | | | | | | | Calling mutex_lock from one thread and then mutex_unlock from another is not permitted. Replace the awkward mutex usage with a mutex and condition variable. llvm.org/pr18061 llvm-svn: 205900
* Fix some doc and comment typosAlp Toker2014-04-0920-27/+27
| | | | llvm-svn: 205899
* [ARM64] Change SYS without a register to an alias to make disassembling more ↵Bradley Smith2014-04-094-22/+12
| | | | | | consistant. llvm-svn: 205898
* [ARM64] Correctly disassemble ISB operand as ISB not DBarrier.Bradley Smith2014-04-092-1/+8
| | | | llvm-svn: 205897
* [ARM64] Properly support both apple and standard syntax for FMOVBradley Smith2014-04-094-13/+19
| | | | llvm-svn: 205896
* [ARM64] Flag setting logical/add/sub immediate instructions don't use SP.Bradley Smith2014-04-093-4/+24
| | | | llvm-svn: 205895
* [ARM64] Conditional branches must always print their condition code, even AL.Bradley Smith2014-04-092-3/+2
| | | | llvm-svn: 205894
* [ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers.Bradley Smith2014-04-092-5/+9
| | | | llvm-svn: 205893
* [ARM64] When printing a pre-indexed address with #0, the ', #0' is not optional.Bradley Smith2014-04-094-13/+67
| | | | llvm-svn: 205892
* [ARM64] Add missing shifted register MVN alias to ORNBradley Smith2014-04-093-0/+21
| | | | llvm-svn: 205891
* [ARM64] SXTW/UXTW are only valid aliases for 32-bit operations.Bradley Smith2014-04-092-1/+7
| | | | llvm-svn: 205890
* [ARM64] Fix canonicalisation of MOVs. MOV is too complex to be modelled by a ↵Bradley Smith2014-04-094-19/+97
| | | | | | dumb alias. llvm-svn: 205889
* [ARM64] Fixup ADR/ADRP parsing such that they accept immediates and all ↵Bradley Smith2014-04-093-41/+99
| | | | | | labels types llvm-svn: 205888
* [ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions.Bradley Smith2014-04-092-2/+4
| | | | llvm-svn: 205887
* [ARM64] Tighten up the special casing in emitting arithmetic extends. UXTW ↵Bradley Smith2014-04-092-8/+10
| | | | | | should only be translated when the instruction uses WSP, not SP. Vice versa for UXTX and 64-bit instructions. llvm-svn: 205886
* [ARM64] Rename LR to the UAL-compliant 'X30'.Bradley Smith2014-04-0910-29/+29
| | | | llvm-svn: 205885
* [ARM64] Rename FP to the UAL-compliant 'X29'.Bradley Smith2014-04-0915-72/+76
| | | | llvm-svn: 205884
* [ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be ↵Bradley Smith2014-04-093-1/+19
| | | | | | zero but should be decoded/disassembled with any value. llvm-svn: 205883
* [ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0.Bradley Smith2014-04-093-8/+29
| | | | llvm-svn: 205882
* [ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have ↵Bradley Smith2014-04-092-1/+8
| | | | | | the top bit of their immediate clear. llvm-svn: 205881
* [ARM64] Scaled fixed-point FCVTZSs should also have bit 29 set to zero.Bradley Smith2014-04-091-1/+1
| | | | llvm-svn: 205880
* [ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1.Bradley Smith2014-04-092-0/+8
| | | | llvm-svn: 205879
* [ARM64] Floating point to fixed point scaled conversions are only available ↵Bradley Smith2014-04-093-78/+22
| | | | | | on fcvtzs and fcvtzu. llvm-svn: 205878
* [ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64.Bradley Smith2014-04-093-1/+22
| | | | llvm-svn: 205877
* [ARM64] Add missing tlbi operands and error for extra/missing register on ↵Bradley Smith2014-04-094-96/+236
| | | | | | tlbi aliases. llvm-svn: 205876
* [ARM64] Rework system register parsing to overcome SPSel clash in MSR variants.Bradley Smith2014-04-093-141/+98
| | | | llvm-svn: 205875
* [ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and ↵Bradley Smith2014-04-093-4/+37
| | | | | | stores, so the unused register fields are set to all-ones canonically but are recognised with any value. llvm-svn: 205874
* [ARM64] Use PStateMapper to ensure that MSRcpsr operands are validated ↵Bradley Smith2014-04-091-2/+7
| | | | | | during disassembly. llvm-svn: 205873
* [ARM64] Remove PrefetchOp and use ARM64PRFM instead.Bradley Smith2014-04-093-81/+14
| | | | llvm-svn: 205872
* [ARM64] Add WZR to isGPR32Register, since every use needs to check for this ↵Bradley Smith2014-04-093-4/+15
| | | | | | anyway. llvm-svn: 205871
* [ARM64] Remove ARM64SYS.Bradley Smith2014-04-091-665/+0
| | | | llvm-svn: 205870
* [ARM64] Move CPSRField and DBarrier operands over to AArch64-style ↵Bradley Smith2014-04-093-51/+46
| | | | | | disassembly and assembly. This removes the last users of namespace ARM64SYS. llvm-svn: 205869
* [ARM64] Switch the decoder, disassembler, instprinter and asmparser over to ↵Bradley Smith2014-04-099-451/+157
| | | | | | using AArch64-style system registers, and fix up test failures discovered in the process. llvm-svn: 205868
* [ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. ↵Bradley Smith2014-04-0917-13/+56
| | | | | | These files are required in the decoder, disassembler and parser, and a layering violation was imminent. llvm-svn: 205867
* [ARM64] Copy the named immediate operand mapping logic and enums from ↵Bradley Smith2014-04-093-0/+1822
| | | | | | AArch64. AArch64's named immediate mapping and parsing is much more advanced than ARM64's. No functionality change - they're currently living side by side while I switch uses over. llvm-svn: 205866
* [ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and ↵Bradley Smith2014-04-093-33/+49
| | | | | | also (for add/sub only) if shift=11. llvm-svn: 205865
* [ARM64] Add support for NV condition code (exists only for valid ↵Bradley Smith2014-04-093-27/+22
| | | | | | assembly/disassembly, equivilant to AL) llvm-svn: 205864
* [ARM64] Add missing 1Q -> 1q vector kind aliasBradley Smith2014-04-092-0/+21
| | | | llvm-svn: 205863
* [ARM64] Add parsing for vector lists such as {v0.8b-v3.8b}Bradley Smith2014-04-092-19/+63
| | | | llvm-svn: 205862
* [ARM64] Correctly alias LSL to UXTW for 32bit instruction variants, rather ↵Bradley Smith2014-04-093-7/+7
| | | | | | than UXTX llvm-svn: 205861
* [ARM64] STRHro and STRBro were not being decoded at all.Bradley Smith2014-04-092-0/+4
| | | | llvm-svn: 205860
* [ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB ↵Bradley Smith2014-04-092-1/+16
| | | | | | instructions is unallocated if shift > 4. llvm-svn: 205859
* [ARM64] Register-offset loads and stores with the 'option' field equal to ↵Bradley Smith2014-04-092-14/+12
| | | | | | 00x or 10x are undefined. llvm-svn: 205858
* Revert "YAMLIO: Encode ambiguous hex strings explicitly"Filipe Cabecinhas2014-04-093-15/+2
| | | | | | | | This reverts commit r205839. It broke several tests in lld. llvm-svn: 205857
* SLPVectorizer: Only vectorize intrinsics whose operands are widened equallyArnold Schwaighofer2014-04-094-26/+100
| | | | | | | | | The vectorizer only knows how to vectorize intrinics by widening all operands by the same factor. Patch by Tyler Nowicki! llvm-svn: 205855
* Extend the check to detect patterns like 'ptr.get() == nullptr'Samuel Benzaquen2014-04-095-42/+102
| | | | | | | | | | | | | | | | | Summary: Extend the check to detect patterns like 'ptr.get() == nullptr' It detects == and != when any argument is a ptr.get() and the other is a nullptr. Only supports standard smart pointer types std::unique_ptr and std::shared_ptr. Does not support the case 'ptr.get() == other.get()' yet. Reviewers: djasper CC: cfe-commits, alexfh Differential Revision: http://llvm-reviews.chandlerc.com/D3294 llvm-svn: 205854
* clang-format: Update flag documentation, and generation script.Daniel Jasper2014-04-093-12/+36
| | | | llvm-svn: 205853
* Declare _DYNAMIC and dl_phdr_info in asan_linux.cc on FreeBSDViktor Kutuzov2014-04-091-1/+5
| | | | llvm-svn: 205852
* clang-format: Treat a trailing comment like a trailing comma in braced lists.Daniel Jasper2014-04-092-8/+14
| | | | | | | | | | | | | | | | | Before: static StructInitInfo module = {MODULE_BUILTIN, /* type */ "streams" /* name */ }; After: static StructInitInfo module = { MODULE_BUILTIN, /* type */ "streams" /* name */ }; This fixes llvm.org/PR19378. llvm-svn: 205851
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