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| author | Bradley Smith <bradley.smith@arm.com> | 2014-04-09 14:43:31 +0000 |
|---|---|---|
| committer | Bradley Smith <bradley.smith@arm.com> | 2014-04-09 14:43:31 +0000 |
| commit | db7b9b17ebba5e0c7ba1307f53e45d86645ad165 (patch) | |
| tree | 4e3a15629d12da2b3807373abd1b65938d739bf5 | |
| parent | 60e7667886043069f544e8543b0fabbeee313bc3 (diff) | |
| download | bcm5719-llvm-db7b9b17ebba5e0c7ba1307f53e45d86645ad165.tar.gz bcm5719-llvm-db7b9b17ebba5e0c7ba1307f53e45d86645ad165.zip | |
[ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have the top bit of their immediate clear.
llvm-svn: 205881
| -rw-r--r-- | llvm/lib/Target/ARM64/ARM64InstrFormats.td | 6 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM64/basic-a64-undefined.txt | 3 |
2 files changed, 8 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM64/ARM64InstrFormats.td b/llvm/lib/Target/ARM64/ARM64InstrFormats.td index f1981bf7499..aeb71a20fb5 100644 --- a/llvm/lib/Target/ARM64/ARM64InstrFormats.td +++ b/llvm/lib/Target/ARM64/ARM64InstrFormats.td @@ -1603,6 +1603,8 @@ multiclass ExtractImm<string asm> { (ARM64Extr GPR32:$Rn, GPR32:$Rm, imm0_31:$imm))]> { let Inst{31} = 0; let Inst{22} = 0; + // imm<5> must be zero. + let imm{5} = 0; } def Xrri : BaseExtractImm<GPR64, imm0_63, asm, [(set GPR64:$Rd, @@ -4849,7 +4851,9 @@ class BaseSIMDBitwiseExtract<bit size, RegisterOperand regtype, ValueType vty, multiclass SIMDBitwiseExtract<string asm> { - def v8i8 : BaseSIMDBitwiseExtract<0, V64, v8i8, asm, ".8b">; + def v8i8 : BaseSIMDBitwiseExtract<0, V64, v8i8, asm, ".8b"> { + let imm{3} = 0; + } def v16i8 : BaseSIMDBitwiseExtract<1, V128, v16i8, asm, ".16b">; } diff --git a/llvm/test/MC/Disassembler/ARM64/basic-a64-undefined.txt b/llvm/test/MC/Disassembler/ARM64/basic-a64-undefined.txt index 21ff82ccccf..c2e3841bb94 100644 --- a/llvm/test/MC/Disassembler/ARM64/basic-a64-undefined.txt +++ b/llvm/test/MC/Disassembler/ARM64/basic-a64-undefined.txt @@ -20,4 +20,7 @@ # UBFM is undefined when s == 0 and imms<5> or immr<5> is 1. # RUN: echo "0x00 0x80 0x00 0x53" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s +# EXT on vectors of i8 must have imm<3> = 0. +# RUN: echo "0x00 0x40 0x00 0x2e" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s + # CHECK: invalid instruction encoding |
