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| author | Bradley Smith <bradley.smith@arm.com> | 2014-04-09 14:43:15 +0000 |
|---|---|---|
| committer | Bradley Smith <bradley.smith@arm.com> | 2014-04-09 14:43:15 +0000 |
| commit | 8f906a3c5fc4429112e6b818452f75443f3fb0df (patch) | |
| tree | 58f6469c8093b7efae3d44baa17da81d56dd57cd | |
| parent | 9f29b726d5101038cd4a7aab11023d058e005026 (diff) | |
| download | bcm5719-llvm-8f906a3c5fc4429112e6b818452f75443f3fb0df.tar.gz bcm5719-llvm-8f906a3c5fc4429112e6b818452f75443f3fb0df.zip | |
[ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64.
llvm-svn: 205877
| -rw-r--r-- | llvm/lib/Target/ARM64/ARM64InstrFormats.td | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp | 13 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM64/canonical-form.txt | 4 |
3 files changed, 22 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM64/ARM64InstrFormats.td b/llvm/lib/Target/ARM64/ARM64InstrFormats.td index 16db02ed275..00658edefa5 100644 --- a/llvm/lib/Target/ARM64/ARM64InstrFormats.td +++ b/llvm/lib/Target/ARM64/ARM64InstrFormats.td @@ -1200,9 +1200,13 @@ class MulHi<bits<3> opc, string asm, SDNode OpNode> let Inst{31-24} = 0b10011011; let Inst{23-21} = opc; let Inst{20-16} = Rm; - let Inst{15-10} = 0b011111; + let Inst{15} = 0; let Inst{9-5} = Rn; let Inst{4-0} = Rd; + + // The Ra field of SMULH and UMULH is unused: it should be assembled as 31 + // (i.e. all bits 1) but is ignored by the processor. + let PostEncoderMethod = "fixMulHigh"; } class MulAccumWAlias<string asm, Instruction inst> diff --git a/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp b/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp index 48172d894aa..5d4651cf274 100644 --- a/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp +++ b/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp @@ -177,6 +177,9 @@ public: SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const; + unsigned fixMulHigh(const MCInst &MI, unsigned EncodedValue, + const MCSubtargetInfo &STI) const; + template<int hasRs, int hasRt2> unsigned fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const; @@ -565,6 +568,16 @@ void ARM64MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS, ++MCNumEmitted; // Keep track of the # of mi's emitted. } +unsigned +ARM64MCCodeEmitter::fixMulHigh(const MCInst &MI, + unsigned EncodedValue, + const MCSubtargetInfo &STI) const { + // The Ra field of SMULH and UMULH is unused: it should be assembled as 31 + // (i.e. all bits 1) but is ignored by the processor. + EncodedValue |= 0x1f << 10; + return EncodedValue; +} + template<int hasRs, int hasRt2> unsigned ARM64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue, diff --git a/llvm/test/MC/Disassembler/ARM64/canonical-form.txt b/llvm/test/MC/Disassembler/ARM64/canonical-form.txt index 6aaa5da3987..ccc93e6e956 100644 --- a/llvm/test/MC/Disassembler/ARM64/canonical-form.txt +++ b/llvm/test/MC/Disassembler/ARM64/canonical-form.txt @@ -3,3 +3,7 @@ 0x00 0x08 0x00 0xc8 # CHECK: stxr w0, x0, [x0] + +0x00 0x00 0x40 0x9b + +# CHECK: smulh x0, x0, x0 |
