summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorBradley Smith <bradley.smith@arm.com>2014-04-09 14:41:49 +0000
committerBradley Smith <bradley.smith@arm.com>2014-04-09 14:41:49 +0000
commit35cadc58c94733a3d2508710c9cc9a52575e3967 (patch)
tree54273d05769b93e5eab6f1173baf353321b4c9ab
parent87c60e00d5f9bca42413f660966b8679634321ae (diff)
downloadbcm5719-llvm-35cadc58c94733a3d2508710c9cc9a52575e3967.tar.gz
bcm5719-llvm-35cadc58c94733a3d2508710c9cc9a52575e3967.zip
[ARM64] STRHro and STRBro were not being decoded at all.
llvm-svn: 205860
-rw-r--r--llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp2
-rw-r--r--llvm/test/MC/Disassembler/ARM64/memory.txt2
2 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp b/llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
index 55267b06409..8e2fa8fee38 100644
--- a/llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
+++ b/llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
@@ -1297,9 +1297,11 @@ static DecodeStatus DecodeRegOffsetLdStInstruction(llvm::MCInst &Inst,
DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
break;
case ARM64::LDRHro:
+ case ARM64::STRHro:
DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
break;
case ARM64::LDRBro:
+ case ARM64::STRBro:
DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
break;
case ARM64::LDRBBro:
diff --git a/llvm/test/MC/Disassembler/ARM64/memory.txt b/llvm/test/MC/Disassembler/ARM64/memory.txt
index 031bfa69032..d0371cfc69f 100644
--- a/llvm/test/MC/Disassembler/ARM64/memory.txt
+++ b/llvm/test/MC/Disassembler/ARM64/memory.txt
@@ -416,11 +416,13 @@
# CHECK: ldr q1, [x1, x2]
# CHECK: ldr q1, [x1, x2, lsl #4]
+ 0x00 0x48 0x20 0x7c
0xe1 0x6b 0x23 0xfc
0xe1 0x5b 0x23 0xfc
0xe1 0x6b 0xa3 0x3c
0xe1 0x5b 0xa3 0x3c
+# CHECK: str h0, [x0, x0, uxtw]
# CHECK: str d1, [sp, x3]
# CHECK: str d1, [sp, x3, uxtw #3]
# CHECK: str q1, [sp, x3]
OpenPOWER on IntegriCloud