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| author | Bradley Smith <bradley.smith@arm.com> | 2014-04-09 14:43:40 +0000 |
|---|---|---|
| committer | Bradley Smith <bradley.smith@arm.com> | 2014-04-09 14:43:40 +0000 |
| commit | 5511f08055d2311cd217a10584d9eaae8a585803 (patch) | |
| tree | aff1d0d597ca71fe57d800cf4128ae41f8914434 | |
| parent | eb4ca04db2b8b57d593a5f768cfbba37d370949e (diff) | |
| download | bcm5719-llvm-5511f08055d2311cd217a10584d9eaae8a585803.tar.gz bcm5719-llvm-5511f08055d2311cd217a10584d9eaae8a585803.zip | |
[ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be zero but should be decoded/disassembled with any value.
llvm-svn: 205883
| -rw-r--r-- | llvm/lib/Target/ARM64/ARM64InstrFormats.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp | 12 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM64/canonical-form.txt | 4 |
3 files changed, 19 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM64/ARM64InstrFormats.td b/llvm/lib/Target/ARM64/ARM64InstrFormats.td index 83a64dc43d7..bd16e12db78 100644 --- a/llvm/lib/Target/ARM64/ARM64InstrFormats.td +++ b/llvm/lib/Target/ARM64/ARM64InstrFormats.td @@ -3502,11 +3502,13 @@ class BaseOneOperandFPComparison<bit signalAllNans, let Inst{31-23} = 0b000111100; let Inst{21} = 1; - let Inst{20-16} = 0b00000; let Inst{15-10} = 0b001000; let Inst{9-5} = Rn; let Inst{4} = signalAllNans; let Inst{3-0} = 0b1000; + + // Rm should be 0b00000 canonically, but we need to accept any value. + let PostEncoderMethod = "fixOneOperandFPComparison"; } let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in diff --git a/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp b/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp index 5d4651cf274..95020e4395e 100644 --- a/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp +++ b/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp @@ -184,6 +184,8 @@ public: fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const; + unsigned fixOneOperandFPComparison(const MCInst &MI, unsigned EncodedValue, + const MCSubtargetInfo &STI) const; }; } // end anonymous namespace @@ -588,4 +590,14 @@ ARM64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI, return EncodedValue; } +unsigned +ARM64MCCodeEmitter::fixOneOperandFPComparison(const MCInst &MI, + unsigned EncodedValue, + const MCSubtargetInfo &STI) const { + // The Rm field of FCMP and friends is unused - it should be assembled + // as 0, but is ignored by the processor. + EncodedValue &= ~(0x1f << 16); + return EncodedValue; +} + #include "ARM64GenMCCodeEmitter.inc" diff --git a/llvm/test/MC/Disassembler/ARM64/canonical-form.txt b/llvm/test/MC/Disassembler/ARM64/canonical-form.txt index ccc93e6e956..3172fd2521f 100644 --- a/llvm/test/MC/Disassembler/ARM64/canonical-form.txt +++ b/llvm/test/MC/Disassembler/ARM64/canonical-form.txt @@ -7,3 +7,7 @@ 0x00 0x00 0x40 0x9b # CHECK: smulh x0, x0, x0 + +0x08 0x20 0x21 0x1e + +# CHECK: fcmp s0, #0.0 |
