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* Speculatively revert r110610 " Make ObjCInterfaceDecl redeclarable,Douglas Gregor2010-08-1120-274/+148
| | | | | | | | and create separate decl nodes for forward declarations and the definition," which appears to be causing significant Objective-C breakage. llvm-svn: 110803
* Consider this code snippet:Bill Wendling2010-08-113-3/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | float t1(int argc) { return (argc == 1123) ? 1.234f : 2.38213f; } We would generate truly awful code on ARM (those with a weak stomach should look away): _t1: movw r1, #1123 movs r2, #1 movs r3, #0 cmp r0, r1 mov.w r0, #0 it eq moveq r0, r2 movs r1, #4 cmp r0, #0 it ne movne r3, r1 adr r0, #LCPI1_0 ldr r0, [r0, r3] bx lr The problem was that legalization was creating a cascade of SELECT_CC nodes, for for the comparison of "argc == 1123" which was fed into a SELECT node for the ?: statement which was itself converted to a SELECT_CC node. This is because the ARM back-end doesn't have custom lowering for SELECT nodes, so it used the default "Expand". I added a fairly simple "LowerSELECT" to the ARM back-end. It takes care of this testcase, but can obviously be expanded to include more cases. Now we generate this, which looks optimal to me: _t1: movw r1, #1123 movs r2, #0 cmp r0, r1 adr r0, #LCPI0_0 it eq moveq r2, #4 ldr r0, [r0, r2] bx lr .align 2 LCPI0_0: .long 1075344593 @ float 2.382130e+00 .long 1067316150 @ float 1.234000e+00 llvm-svn: 110799
* Report error if codegen tries to instantiate a ARM target when the cpu does ↵Evan Cheng2010-08-116-13/+15
| | | | | | support it. e.g. cortex-m* processors. llvm-svn: 110798
* ArchV7M implies HW division instructions.Evan Cheng2010-08-111-3/+3
| | | | llvm-svn: 110797
* ArchV6T2, V7A, and V7M implies Thumb2; Archv7A implies NEON.Evan Cheng2010-08-111-11/+10
| | | | llvm-svn: 110796
* Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.)Evan Cheng2010-08-113-38/+42
| | | | llvm-svn: 110795
* MC/ARM: Add basic support for handling predication by parsing it out of the ↵Daniel Dunbar2010-08-112-1/+52
| | | | | | mnemonic into a separate operand form. llvm-svn: 110794
* MC/ARM: Split mnemonic on '.' characters.Daniel Dunbar2010-08-111-3/+16
| | | | llvm-svn: 110793
* MC/ARM: Fill in ARMOperand::dump a bit.Daniel Dunbar2010-08-111-1/+21
| | | | llvm-svn: 110792
* llvm-mc: Add -show-inst-operands, for dumping the parsed instruction ↵Daniel Dunbar2010-08-114-1/+26
| | | | | | representation before matching. llvm-svn: 110791
* MCAsmParser: Add dump() hook to MCParsedAsmOperand.Daniel Dunbar2010-08-114-6/+10
| | | | llvm-svn: 110790
* tblgen/AsmMatcher: Treat '.' in assembly strings as a token separator.Daniel Dunbar2010-08-111-0/+8
| | | | llvm-svn: 110789
* MC/ARM: Add an ARMOperand class for condition codes.Daniel Dunbar2010-08-112-4/+30
| | | | llvm-svn: 110788
* Really control isel of barrier instructions with cpu feature.Evan Cheng2010-08-112-4/+4
| | | | llvm-svn: 110787
* Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bitEvan Cheng2010-08-112-5/+17
| | | | | | instructions: dmb, dsb, isb, msr, and mrs. llvm-svn: 110786
* - Add subtarget feature -mattr=+db which determine whether an ARM cpu has theEvan Cheng2010-08-119-55/+88
| | | | | | | | | memory and synchronization barrier dmb and dsb instructions. - Change instruction names to something more sensible (matching name of actual instructions). - Added tests for memory barrier codegen. llvm-svn: 110785
* MemRegion can refer to ASTContext without external help.Zhongxing Xu2010-08-1118-85/+72
| | | | llvm-svn: 110784
* MC/ARM: Switch to using the generated match functions instead of stub ↵Daniel Dunbar2010-08-111-81/+30
| | | | | | implementations. llvm-svn: 110783
* MC/ARM: Enable generation of the ARM asm matcher, not that it can do much.Daniel Dunbar2010-08-112-2/+3
| | | | llvm-svn: 110782
* ARM: Mark some disassembler only instructions as not available for matching --Daniel Dunbar2010-08-111-0/+4
| | | | | | | for some reason they have a very odd MCInst form where the operands overlap, but I haven't dug in to find out why yet. llvm-svn: 110781
* ARM: Quote $p in an asm string.Daniel Dunbar2010-08-111-2/+2
| | | | llvm-svn: 110780
* tblgen/AsmMatcher: Downgrade instructions with tied operands to a debug-only ↵Daniel Dunbar2010-08-111-3/+6
| | | | | | warning, for now. llvm-svn: 110779
* Improve indentation.Owen Anderson2010-08-111-27/+28
| | | | llvm-svn: 110778
* Added support for persistent variables to theSean Callanan2010-08-1112-64/+444
| | | | | | | | | | | | | | | | | | | | | | | | | expression parser. It is now possible to type: (lldb) expr int $i = 5; $i + 1 (int) 6 (lldb) expr $i + 2 (int) 7 The skeleton for automatic result variables is also implemented. The changes affect: - the process, which now contains a ClangPersistentVariables object that holds persistent variables associated with it - the expression parser, which now uses the persistent variables during variable lookup - TaggedASTType, where I loaded some commonly used tags into a header so that they are interchangeable between different clients of the class llvm-svn: 110777
* tests: Add a missing -Xclang.Daniel Dunbar2010-08-111-1/+1
| | | | llvm-svn: 110776
* ARM: Recognize single precision float register names.Daniel Dunbar2010-08-112-1/+25
| | | | | | | - We don't recognize double or NEON register names yet -- we don't have the infrastructure to generate the right clobbers for them. llvm-svn: 110775
* ARM: Swap which registers we consider real / aliases to match LLVM and llvm-gcc.Daniel Dunbar2010-08-112-6/+13
| | | | llvm-svn: 110774
* Improve our handling of user-defined conversions when computingDouglas Gregor2010-08-115-79/+150
| | | | | | | | | | | | | | | | | | | | | | implicit conversion sequences. In particular, model the "standard conversion" from a class to its own type (or a base type) directly as a standard conversion in the normal path *without* trying to determine if there is a valid copy constructor. This appears to match the intent of C++ [over.best.ics]p6 and more closely matches GCC and EDG. As part of this, model non-lvalue reference initialization via user-defined conversion in overloading the same way we handle it in InitializationSequence, separating the "general user-defined conversion" and "conversion to compatible class type" cases. The churn in the overload-call-copycon.cpp test case is because the test case was originally wrong; it assumed that we should do more checking for copy constructors that we actually should, which affected overload resolution. Fixes PR7055. Bootstrapped okay. llvm-svn: 110773
* Remove AVX 256-bit cast intrinsics now that clang is using ↵Bruno Cardoso Lopes2010-08-111-12/+0
| | | | | | __builtin_shufflevector for those llvm-svn: 110772
* Remove 256-bit cast built-ins and make the AVX intrinsic call llvm ↵Bruno Cardoso Lopes2010-08-113-18/+9
| | | | | | __builtin_shufflevector with the appropriate arguments llvm-svn: 110771
* Make this test a little less dependent on exact optimizer results.John McCall2010-08-111-6/+6
| | | | llvm-svn: 110770
* Remove AVX 256-bit unpack and interleave intrinsics now that clang is using ↵Bruno Cardoso Lopes2010-08-111-16/+0
| | | | | | __builtin_shufflevector for those llvm-svn: 110769
* Remove 256-bit unpack built-ins and make the AVX intrinsic call llvm ↵Bruno Cardoso Lopes2010-08-113-12/+4
| | | | | | __builtin_shufflevector with the appropriate arguments llvm-svn: 110768
* Remove AVX 256-bit shuffle intrinsics now that clang is using ↵Bruno Cardoso Lopes2010-08-111-10/+0
| | | | | | __builtin_shufflevector for those llvm-svn: 110767
* Remove 256-bit shuffle built-ins and make the AVX intrinsic call llvm ↵Bruno Cardoso Lopes2010-08-113-15/+13
| | | | | | __builtin_shufflevector with the appropriate arguments llvm-svn: 110766
* Update test to match output of optimize compares for ARM.Bill Wendling2010-08-111-4/+2
| | | | llvm-svn: 110765
* Fix for pr7869, inline asm mult-alt constraints.John Thompson2010-08-112-5/+48
| | | | llvm-svn: 110764
* CMake: corrections on LLVM.cmake external services.Oscar Fuentes2010-08-113-4/+15
| | | | llvm-svn: 110763
* Handle ARM compares as well as converting for ARM adds, subs, and thumb2's adds.Bill Wendling2010-08-111-0/+5
| | | | llvm-svn: 110762
* Mark ARM compare instructions as isCompare.Bill Wendling2010-08-111-1/+1
| | | | llvm-svn: 110761
* Fix a bug in @finally emission in both the fragile and non-fragile EH schemesJohn McCall2010-08-113-5/+77
| | | | | | | | | where we weren't accounting for the possibility that a @finally block might have internal cleanups and therefore might write to the cleanup destination slot. Fixes <rdar://problem/8293901>. llvm-svn: 110760
* Make it possible to set the cpu used for codegen.Rafael Espindola2010-08-115-1/+29
| | | | llvm-svn: 110759
* When analyzing loop exit conditions combined with and and or, don'tDan Gohman2010-08-112-16/+52
| | | | | | | make any assumptions about when the two conditions will agree on when to permit the loop to exit. This fixes PR7845. llvm-svn: 110758
* lto: Fix an inverted conditional which prevented the addition of symbols scrapedDaniel Dunbar2010-08-111-1/+1
| | | | | | | | from inline assembly, except in cases where they had already been seen (in which case they would get added twice). - I can't see how this ever worked... llvm-svn: 110757
* lto: Fix gratuitous memory leaks.Daniel Dunbar2010-08-111-3/+3
| | | | llvm-svn: 110756
* Have GRCoreEngine record the blocks where analysis was aborted because we ↵Ted Kremenek2010-08-112-12/+22
| | | | | | visited a block too many times along a given path. This is to support the unreachable code analysis. llvm-svn: 110755
* Add a separate ARM instruction format for Saturate instructions.Bob Wilson2010-08-117-181/+208
| | | | | | | | | (I discovered 2 more copies of the ARM instruction format list, bringing the total to 4!! Two of them were already out of sync. I haven't yet gotten into the disassembler enough to know the best way to fix this, but something needs to be done.) Add support for encoding these instructions. llvm-svn: 110754
* Avoid multiple definition warnings when both config.h andOscar Fuentes2010-08-102-0/+12
| | | | | | | | llvm-config.h are included. This is the cmake counterpart of r110547. See bug #7809. llvm-svn: 110753
* lto: Reduce nesting.Daniel Dunbar2010-08-101-56/+57
| | | | llvm-svn: 110752
* LTOModule.cpp: Fix numerous style issues.Daniel Dunbar2010-08-101-413/+390
| | | | llvm-svn: 110751
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