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| author | Daniel Dunbar <daniel@zuster.org> | 2010-08-11 04:46:13 +0000 |
|---|---|---|
| committer | Daniel Dunbar <daniel@zuster.org> | 2010-08-11 04:46:13 +0000 |
| commit | 07cc87438f02488036c4e62ba9e9e8ec0f5e8a41 (patch) | |
| tree | 761b971767136a4c4fa116338dc63304ff594ff2 | |
| parent | 740c50385c83318006bdffe428749b6ee658301e (diff) | |
| download | bcm5719-llvm-07cc87438f02488036c4e62ba9e9e8ec0f5e8a41.tar.gz bcm5719-llvm-07cc87438f02488036c4e62ba9e9e8ec0f5e8a41.zip | |
ARM: Mark some disassembler only instructions as not available for matching --
for some reason they have a very odd MCInst form where the operands overlap, but
I haven't dug in to find out why yet.
llvm-svn: 110781
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrVFP.td | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrVFP.td b/llvm/lib/Target/ARM/ARMInstrVFP.td index d15544420b8..490522b6a05 100644 --- a/llvm/lib/Target/ARM/ARMInstrVFP.td +++ b/llvm/lib/Target/ARM/ARMInstrVFP.td @@ -461,6 +461,7 @@ let Constraints = "$a = $dst" in { // FP to Fixed-Point: +let isCodeGenOnly = 1 in { def VTOSHS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 0, (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits), IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", @@ -500,9 +501,11 @@ def VTOULD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 1, (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits), IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", [/* For disassembly only; pattern left blank */]>; +} // Fixed-Point to FP: +let isCodeGenOnly = 1 in { def VSHTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 0, (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits), IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", @@ -542,6 +545,7 @@ def VULTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 1, (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits), IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", [/* For disassembly only; pattern left blank */]>; +} } // End of 'let Constraints = "$src = $dst" in' |
