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| author | Puyan Lotfi <puyan@puyan.org> | 2018-01-31 22:04:26 +0000 |
|---|---|---|
| committer | Puyan Lotfi <puyan@puyan.org> | 2018-01-31 22:04:26 +0000 |
| commit | 43e94b15ea0c180ebb0fd3e6b697dac4564aaf60 (patch) | |
| tree | f7934a17bdee8aeebc4f8c00769b5fdd6bd1b9ff /llvm/test/CodeGen/MIR | |
| parent | de07acb9a53066cb9c2a3e4bc4edd7be06db17d1 (diff) | |
| download | bcm5719-llvm-43e94b15ea0c180ebb0fd3e6b697dac4564aaf60.tar.gz bcm5719-llvm-43e94b15ea0c180ebb0fd3e6b697dac4564aaf60.zip | |
Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:
http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html
In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.
llvm-svn: 323922
Diffstat (limited to 'llvm/test/CodeGen/MIR')
159 files changed, 1434 insertions, 1434 deletions
diff --git a/llvm/test/CodeGen/MIR/AArch64/addrspace-memoperands.mir b/llvm/test/CodeGen/MIR/AArch64/addrspace-memoperands.mir index a7906e04ca8..c33e48b882f 100644 --- a/llvm/test/CodeGen/MIR/AArch64/addrspace-memoperands.mir +++ b/llvm/test/CodeGen/MIR/AArch64/addrspace-memoperands.mir @@ -13,14 +13,14 @@ body: | bb.0: ; CHECK-LABEL: name: addrspace_memoperands - ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0 + ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load 8, addrspace 1) ; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4, align 2, addrspace 3) ; CHECK: G_STORE [[LOAD]](s64), [[COPY]](p0) :: (store 8, addrspace 1) ; CHECK: G_STORE [[LOAD1]](s32), [[COPY]](p0) :: (store 4, align 2, addrspace 3) ; CHECK: G_STORE [[LOAD1]](s32), [[COPY]](p0) :: (store 4) ; CHECK: RET_ReallyLR - %0:_(p0) = COPY %x0 + %0:_(p0) = COPY $x0 %1:_(s64) = G_LOAD %0(p0) :: (load 8, addrspace 1) %2:_(s32) = G_LOAD %0(p0) :: (load 4, align 2, addrspace 3) G_STORE %1(s64), %0(p0) :: (store 8, addrspace 1) diff --git a/llvm/test/CodeGen/MIR/AArch64/atomic-memoperands.mir b/llvm/test/CodeGen/MIR/AArch64/atomic-memoperands.mir index 2dfb61c53d5..bb9f920bedd 100644 --- a/llvm/test/CodeGen/MIR/AArch64/atomic-memoperands.mir +++ b/llvm/test/CodeGen/MIR/AArch64/atomic-memoperands.mir @@ -14,7 +14,7 @@ body: | bb.0: ; CHECK-LABEL: name: atomic_memoperands - ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0 + ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load unordered 8) ; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load monotonic 4) ; CHECK: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load acquire 2) @@ -22,7 +22,7 @@ body: | ; CHECK: G_STORE [[LOAD1]](s32), [[COPY]](p0) :: (store acq_rel 4) ; CHECK: G_STORE [[LOAD]](s64), [[COPY]](p0) :: (store syncscope("singlethread") seq_cst 8) ; CHECK: RET_ReallyLR - %0:_(p0) = COPY %x0 + %0:_(p0) = COPY $x0 %1:_(s64) = G_LOAD %0(p0) :: (load unordered 8) %2:_(s32) = G_LOAD %0(p0) :: (load monotonic 4) %3:_(s16) = G_LOAD %0(p0) :: (load acquire 2) diff --git a/llvm/test/CodeGen/MIR/AArch64/cfi.mir b/llvm/test/CodeGen/MIR/AArch64/cfi.mir index 2a39c272ec6..747d58eb320 100644 --- a/llvm/test/CodeGen/MIR/AArch64/cfi.mir +++ b/llvm/test/CodeGen/MIR/AArch64/cfi.mir @@ -17,26 +17,26 @@ name: trivial_fp_func # CHECK-LABEL: name: trivial_fp_func body: | bb.0.entry: - ; CHECK: CFI_INSTRUCTION def_cfa %w29, 16 - frame-setup CFI_INSTRUCTION def_cfa %w29, 16 - ; CHECK: CFI_INSTRUCTION def_cfa_register %w29 - frame-setup CFI_INSTRUCTION def_cfa_register %w29 + ; CHECK: CFI_INSTRUCTION def_cfa $w29, 16 + frame-setup CFI_INSTRUCTION def_cfa $w29, 16 + ; CHECK: CFI_INSTRUCTION def_cfa_register $w29 + frame-setup CFI_INSTRUCTION def_cfa_register $w29 ; CHECK: CFI_INSTRUCTION def_cfa_offset -8 frame-setup CFI_INSTRUCTION def_cfa_offset -8 - ; CHECK: CFI_INSTRUCTION offset %w30, -8 - frame-setup CFI_INSTRUCTION offset %w30, -8 - ; CHECK: CFI_INSTRUCTION rel_offset %w30, -8 - frame-setup CFI_INSTRUCTION rel_offset %w30, -8 + ; CHECK: CFI_INSTRUCTION offset $w30, -8 + frame-setup CFI_INSTRUCTION offset $w30, -8 + ; CHECK: CFI_INSTRUCTION rel_offset $w30, -8 + frame-setup CFI_INSTRUCTION rel_offset $w30, -8 ; CHECK: CFI_INSTRUCTION adjust_cfa_offset -8 frame-setup CFI_INSTRUCTION adjust_cfa_offset -8 - CFI_INSTRUCTION restore %w30 - ; CHECK: CFI_INSTRUCTION restore %w30 - CFI_INSTRUCTION undefined %w30 - ; CHECK: CFI_INSTRUCTION undefined %w30 - CFI_INSTRUCTION same_value %w29 - ; CHECK: CFI_INSTRUCTION same_value %w29 - CFI_INSTRUCTION register %w20, %w30 - ; CHECK: CFI_INSTRUCTION register %w20, %w30 + CFI_INSTRUCTION restore $w30 + ; CHECK: CFI_INSTRUCTION restore $w30 + CFI_INSTRUCTION undefined $w30 + ; CHECK: CFI_INSTRUCTION undefined $w30 + CFI_INSTRUCTION same_value $w29 + ; CHECK: CFI_INSTRUCTION same_value $w29 + CFI_INSTRUCTION register $w20, $w30 + ; CHECK: CFI_INSTRUCTION register $w20, $w30 CFI_INSTRUCTION remember_state ; CHECK: CFI_INSTRUCTION remember_state CFI_INSTRUCTION restore_state diff --git a/llvm/test/CodeGen/MIR/AArch64/expected-target-flag-name.mir b/llvm/test/CodeGen/MIR/AArch64/expected-target-flag-name.mir index f94f09a485d..31489ab356e 100644 --- a/llvm/test/CodeGen/MIR/AArch64/expected-target-flag-name.mir +++ b/llvm/test/CodeGen/MIR/AArch64/expected-target-flag-name.mir @@ -16,8 +16,8 @@ name: sub_small body: | bb.0.entry: - %x8 = ADRP target-flags(aarch64-page) @var_i32 + $x8 = ADRP target-flags(aarch64-page) @var_i32 ; CHECK: [[@LINE+1]]:60: expected the name of the target flag - %w0 = LDRWui killed %x8, target-flags(aarch64-pageoff, ) @var_i32 - RET_ReallyLR implicit %w0 + $w0 = LDRWui killed $x8, target-flags(aarch64-pageoff, ) @var_i32 + RET_ReallyLR implicit $w0 ... diff --git a/llvm/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir b/llvm/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir index af785bcb10a..9236b69fb70 100644 --- a/llvm/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir +++ b/llvm/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir @@ -14,8 +14,8 @@ registers: - { id: 0, class: _ } body: | bb.0: - liveins: %w0 + liveins: $w0 ; ERR: generic virtual registers must have a type ; ERR-NEXT: %0 - %0 = G_ADD i32 %w0, %w0 + %0 = G_ADD i32 $w0, $w0 ... diff --git a/llvm/test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir b/llvm/test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir index f177b91da55..1cf5e385485 100644 --- a/llvm/test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir +++ b/llvm/test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir @@ -15,8 +15,8 @@ registers: - { id: 0, class: gpr } body: | bb.0: - liveins: %w0 + liveins: $w0 ; ERR: generic virtual registers must have a type ; ERR-NEXT: %0 - %0 = G_ADD i32 %w0, %w0 + %0 = G_ADD i32 $w0, $w0 ... diff --git a/llvm/test/CodeGen/MIR/AArch64/intrinsics.mir b/llvm/test/CodeGen/MIR/AArch64/intrinsics.mir index b158c21b00e..d7361ea3657 100644 --- a/llvm/test/CodeGen/MIR/AArch64/intrinsics.mir +++ b/llvm/test/CodeGen/MIR/AArch64/intrinsics.mir @@ -9,10 +9,10 @@ ... --- # Completely invalid code, but it checks that intrinsics round-trip properly. -# CHECK: %x0 = COPY intrinsic(@llvm.returnaddress) +# CHECK: $x0 = COPY intrinsic(@llvm.returnaddress) name: use_intrin body: | bb.0: - %x0 = COPY intrinsic(@llvm.returnaddress) + $x0 = COPY intrinsic(@llvm.returnaddress) RET_ReallyLR ... diff --git a/llvm/test/CodeGen/MIR/AArch64/invalid-target-flag-name.mir b/llvm/test/CodeGen/MIR/AArch64/invalid-target-flag-name.mir index e2a25753531..7886ae21793 100644 --- a/llvm/test/CodeGen/MIR/AArch64/invalid-target-flag-name.mir +++ b/llvm/test/CodeGen/MIR/AArch64/invalid-target-flag-name.mir @@ -16,8 +16,8 @@ name: sub_small body: | bb.0.entry: - %x8 = ADRP target-flags(aarch64-page) @var_i32 + $x8 = ADRP target-flags(aarch64-page) @var_i32 ; CHECK: [[@LINE+1]]:60: use of undefined target flag 'ncc' - %w0 = LDRWui killed %x8, target-flags(aarch64-pageoff, ncc) @var_i32 - RET_ReallyLR implicit %w0 + $w0 = LDRWui killed $x8, target-flags(aarch64-pageoff, ncc) @var_i32 + RET_ReallyLR implicit $w0 ... diff --git a/llvm/test/CodeGen/MIR/AArch64/invalid-target-memoperands.mir b/llvm/test/CodeGen/MIR/AArch64/invalid-target-memoperands.mir index 731d7165b9d..67052e25e09 100644 --- a/llvm/test/CodeGen/MIR/AArch64/invalid-target-memoperands.mir +++ b/llvm/test/CodeGen/MIR/AArch64/invalid-target-memoperands.mir @@ -12,7 +12,7 @@ name: target_memoperands_error body: | bb.0: - %0:_(p0) = COPY %x0 + %0:_(p0) = COPY $x0 ; CHECK: [[@LINE+1]]:35: use of undefined target MMO flag 'aarch64-invalid' %1:_(s64) = G_LOAD %0(p0) :: ("aarch64-invalid" load 8) RET_ReallyLR diff --git a/llvm/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir b/llvm/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir index e19b618123d..5f4bd9897d8 100644 --- a/llvm/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir +++ b/llvm/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir @@ -17,12 +17,12 @@ name: trivial_fp_func body: | bb.0.entry: - liveins: %lr, %fp, %lr, %fp + liveins: $lr, $fp, $lr, $fp - %sp = frame-setup STPXpre killed %fp, killed %lr, %sp, -2 - %fp = frame-setup ADDXri %sp, 0, 0 - BL @foo, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp - ; CHECK: %sp, %fp, %lr = LDPXpost %sp, 2 - %sp, %fp, %lr = LDPXpost %sp, 2 + $sp = frame-setup STPXpre killed $fp, killed $lr, $sp, -2 + $fp = frame-setup ADDXri $sp, 0, 0 + BL @foo, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp + ; CHECK: $sp, $fp, $lr = LDPXpost $sp, 2 + $sp, $fp, $lr = LDPXpost $sp, 2 RET_ReallyLR ... diff --git a/llvm/test/CodeGen/MIR/AArch64/register-operand-bank.mir b/llvm/test/CodeGen/MIR/AArch64/register-operand-bank.mir index d2f99933a35..3da69342c93 100644 --- a/llvm/test/CodeGen/MIR/AArch64/register-operand-bank.mir +++ b/llvm/test/CodeGen/MIR/AArch64/register-operand-bank.mir @@ -12,9 +12,9 @@ name: func body: | bb.0: - %0 : gpr(s64) = COPY %x9 - %x9 = COPY %0 + %0 : gpr(s64) = COPY $x9 + $x9 = COPY %0 - %3 : fpr(s64) = COPY %d0 - %d1 = COPY %3 : fpr + %3 : fpr(s64) = COPY $d0 + $d1 = COPY %3 : fpr ... diff --git a/llvm/test/CodeGen/MIR/AArch64/swp.mir b/llvm/test/CodeGen/MIR/AArch64/swp.mir index 4a31ab43535..4c39b4aa931 100644 --- a/llvm/test/CodeGen/MIR/AArch64/swp.mir +++ b/llvm/test/CodeGen/MIR/AArch64/swp.mir @@ -18,16 +18,16 @@ registers: - { id: 1, class: gpr32 } - { id: 2, class: gpr32 } liveins: - - { reg: '%x0', virtual-reg: '%0' } + - { reg: '$x0', virtual-reg: '%0' } body: | bb.0.entry: - liveins: %x0 + liveins: $x0 ; CHECK-LABEL: swp ; CHECK: {{[0-9]+}}:gpr32 = SWPW killed %1, %0 :: (volatile load store monotonic 4 on %ir.addr) - %0:gpr64common = COPY %x0 + %0:gpr64common = COPY $x0 %1:gpr32 = MOVi32imm 1 %2:gpr32 = SWPW killed %1, %0 :: (volatile load store monotonic 4 on %ir.addr) - %w0 = COPY %2 - RET_ReallyLR implicit %w0 + $w0 = COPY %2 + RET_ReallyLR implicit $w0 ... diff --git a/llvm/test/CodeGen/MIR/AArch64/target-flags.mir b/llvm/test/CodeGen/MIR/AArch64/target-flags.mir index e0a41015531..16f9b43ca2f 100644 --- a/llvm/test/CodeGen/MIR/AArch64/target-flags.mir +++ b/llvm/test/CodeGen/MIR/AArch64/target-flags.mir @@ -21,19 +21,19 @@ name: sub_small body: | bb.0.entry: - ; CHECK: %x8 = ADRP target-flags(aarch64-page) @var_i32 - ; CHECK-NEXT: %x9 = ADRP target-flags(aarch64-page) @var_i64 - ; CHECK-NEXT: %w10 = LDRWui %x8, target-flags(aarch64-pageoff, aarch64-nc) @var_i32 - ; CHECK-NEXT: %x11 = LDRXui %x9, target-flags(aarch64-pageoff, aarch64-got, aarch64-nc) @var_i64 - ; CHECK: STRWui killed %w10, killed %x8, target-flags(aarch64-nc) @var_i32 - ; CHECK: STRXui killed %x11, killed %x9, target-flags(aarch64-pageoff, aarch64-nc) @var_i64 - %x8 = ADRP target-flags(aarch64-page) @var_i32 - %x9 = ADRP target-flags(aarch64-page) @var_i64 - %w10 = LDRWui %x8, target-flags(aarch64-pageoff, aarch64-nc) @var_i32 - %x11 = LDRXui %x9, target-flags(aarch64-pageoff, aarch64-got, aarch64-nc) @var_i64 - %w10 = SUBWri killed %w10, 4095, 0 - %x11 = SUBXri killed %x11, 52, 0 - STRWui killed %w10, killed %x8, target-flags(aarch64-nc) @var_i32 - STRXui killed %x11, killed %x9, target-flags(aarch64-pageoff, aarch64-nc) @var_i64 + ; CHECK: $x8 = ADRP target-flags(aarch64-page) @var_i32 + ; CHECK-NEXT: $x9 = ADRP target-flags(aarch64-page) @var_i64 + ; CHECK-NEXT: $w10 = LDRWui $x8, target-flags(aarch64-pageoff, aarch64-nc) @var_i32 + ; CHECK-NEXT: $x11 = LDRXui $x9, target-flags(aarch64-pageoff, aarch64-got, aarch64-nc) @var_i64 + ; CHECK: STRWui killed $w10, killed $x8, target-flags(aarch64-nc) @var_i32 + ; CHECK: STRXui killed $x11, killed $x9, target-flags(aarch64-pageoff, aarch64-nc) @var_i64 + $x8 = ADRP target-flags(aarch64-page) @var_i32 + $x9 = ADRP target-flags(aarch64-page) @var_i64 + $w10 = LDRWui $x8, target-flags(aarch64-pageoff, aarch64-nc) @var_i32 + $x11 = LDRXui $x9, target-flags(aarch64-pageoff, aarch64-got, aarch64-nc) @var_i64 + $w10 = SUBWri killed $w10, 4095, 0 + $x11 = SUBXri killed $x11, 52, 0 + STRWui killed $w10, killed $x8, target-flags(aarch64-nc) @var_i32 + STRXui killed $x11, killed $x9, target-flags(aarch64-pageoff, aarch64-nc) @var_i64 RET_ReallyLR ... diff --git a/llvm/test/CodeGen/MIR/AArch64/target-memoperands.mir b/llvm/test/CodeGen/MIR/AArch64/target-memoperands.mir index a3442f25135..ab79611a5c3 100644 --- a/llvm/test/CodeGen/MIR/AArch64/target-memoperands.mir +++ b/llvm/test/CodeGen/MIR/AArch64/target-memoperands.mir @@ -14,13 +14,13 @@ body: | bb.0: ; CHECK-LABEL: name: target_memoperands - ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0 + ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: ("aarch64-suppress-pair" load 8) ; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: ("aarch64-strided-access" load 4) ; CHECK: G_STORE [[LOAD]](s64), [[COPY]](p0) :: ("aarch64-suppress-pair" store 8) ; CHECK: G_STORE [[LOAD1]](s32), [[COPY]](p0) :: ("aarch64-strided-access" store 4) ; CHECK: RET_ReallyLR - %0:_(p0) = COPY %x0 + %0:_(p0) = COPY $x0 %1:_(s64) = G_LOAD %0(p0) :: ("aarch64-suppress-pair" load 8) %2:_(s32) = G_LOAD %0(p0) :: ("aarch64-strided-access" load 4) G_STORE %1(s64), %0(p0) :: ("aarch64-suppress-pair" store 8) diff --git a/llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir b/llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir index 5da98fb9c2d..94a9db7e953 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir +++ b/llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir @@ -20,30 +20,30 @@ --- name: float liveins: - - { reg: '%sgpr0_sgpr1' } + - { reg: '$sgpr0_sgpr1' } frameInfo: maxAlignment: 8 body: | bb.0.entry: - liveins: %sgpr0_sgpr1 + liveins: $sgpr0_sgpr1 - %sgpr2_sgpr3 = S_GETPC_B64 + $sgpr2_sgpr3 = S_GETPC_B64 ; CHECK: [[@LINE+1]]:45: expected the name of the target index - %sgpr2 = S_ADD_U32 %sgpr2, target-index(0), implicit-def %scc, implicit-def %scc - %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc - %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc - %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11 - %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc - %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc - %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc - %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc - %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc - %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc - %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0 - %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9 - %sgpr7 = S_MOV_B32 61440 - %sgpr6 = S_MOV_B32 -1 - %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec - BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec + $sgpr2 = S_ADD_U32 $sgpr2, target-index(0), implicit-def $scc, implicit-def $scc + $sgpr3 = S_ADDC_U32 $sgpr3, 0, implicit-def $scc, implicit $scc, implicit-def $scc, implicit $scc + $sgpr4_sgpr5 = S_LSHR_B64 $sgpr2_sgpr3, 32, implicit-def dead $scc + $sgpr6 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 11 + $sgpr7 = S_ASHR_I32 $sgpr6, 31, implicit-def dead $scc + $sgpr6_sgpr7 = S_LSHL_B64 $sgpr6_sgpr7, 2, implicit-def dead $scc + $sgpr2 = S_ADD_U32 $sgpr2, @float_gv, implicit-def $scc + $sgpr3 = S_ADDC_U32 $sgpr4, 0, implicit-def dead $scc, implicit $scc + $sgpr4 = S_ADD_U32 $sgpr2, $sgpr6, implicit-def $scc + $sgpr5 = S_ADDC_U32 $sgpr3, $sgpr7, implicit-def dead $scc, implicit $scc + $sgpr2 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 0 + $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 9 + $sgpr7 = S_MOV_B32 61440 + $sgpr6 = S_MOV_B32 -1 + $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec + BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec S_ENDPGM ... diff --git a/llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir b/llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir index 8cffc86373a..ecee2436eb9 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir +++ b/llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir @@ -20,30 +20,30 @@ --- name: float liveins: - - { reg: '%sgpr0_sgpr1' } + - { reg: '$sgpr0_sgpr1' } frameInfo: maxAlignment: 8 body: | bb.0.entry: - liveins: %sgpr0_sgpr1 + liveins: $sgpr0_sgpr1 - %sgpr2_sgpr3 = S_GETPC_B64 + $sgpr2_sgpr3 = S_GETPC_B64 ; CHECK: [[@LINE+1]]:45: use of undefined target index 'constdata-start' - %sgpr2 = S_ADD_U32 %sgpr2, target-index(constdata-start), implicit-def %scc, implicit-def %scc - %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc - %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc - %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11 - %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc - %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc - %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc - %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc - %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc - %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc - %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0 - %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9 - %sgpr7 = S_MOV_B32 61440 - %sgpr6 = S_MOV_B32 -1 - %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec - BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec + $sgpr2 = S_ADD_U32 $sgpr2, target-index(constdata-start), implicit-def $scc, implicit-def $scc + $sgpr3 = S_ADDC_U32 $sgpr3, 0, implicit-def $scc, implicit $scc, implicit-def $scc, implicit $scc + $sgpr4_sgpr5 = S_LSHR_B64 $sgpr2_sgpr3, 32, implicit-def dead $scc + $sgpr6 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 11 + $sgpr7 = S_ASHR_I32 $sgpr6, 31, implicit-def dead $scc + $sgpr6_sgpr7 = S_LSHL_B64 $sgpr6_sgpr7, 2, implicit-def dead $scc + $sgpr2 = S_ADD_U32 $sgpr2, @float_gv, implicit-def $scc + $sgpr3 = S_ADDC_U32 $sgpr4, 0, implicit-def dead $scc, implicit $scc + $sgpr4 = S_ADD_U32 $sgpr2, $sgpr6, implicit-def $scc + $sgpr5 = S_ADDC_U32 $sgpr3, $sgpr7, implicit-def dead $scc, implicit $scc + $sgpr2 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 0 + $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 9 + $sgpr7 = S_MOV_B32 61440 + $sgpr6 = S_MOV_B32 -1 + $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec + BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec S_ENDPGM ... diff --git a/llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir b/llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir index 1f29fb156fb..d3b919d43a3 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir +++ b/llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir @@ -42,9 +42,9 @@ !0 = !{i32 1} # GCN-LABEL: name: syncscopes -# GCN: FLAT_STORE_DWORD killed %vgpr0_vgpr1, killed %vgpr2, 0, -1, 0, implicit %exec, implicit %flat_scr :: (volatile non-temporal store syncscope("agent") seq_cst 4 into %ir.agent_out, addrspace 4) -# GCN: FLAT_STORE_DWORD killed %vgpr0_vgpr1, killed %vgpr2, 0, -1, 0, implicit %exec, implicit %flat_scr :: (volatile non-temporal store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out, addrspace 4) -# GCN: FLAT_STORE_DWORD killed %vgpr0_vgpr1, killed %vgpr2, 0, -1, 0, implicit %exec, implicit %flat_scr :: (volatile non-temporal store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out, addrspace 4) +# GCN: FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("agent") seq_cst 4 into %ir.agent_out, addrspace 4) +# GCN: FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out, addrspace 4) +# GCN: FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out, addrspace 4) ... --- name: syncscopes @@ -55,7 +55,7 @@ regBankSelected: false selected: false tracksRegLiveness: true liveins: - - { reg: '%sgpr4_sgpr5' } + - { reg: '$sgpr4_sgpr5' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false @@ -71,30 +71,30 @@ frameInfo: hasMustTailInVarArgFunc: false body: | bb.0.entry: - liveins: %sgpr4_sgpr5 + liveins: $sgpr4_sgpr5 S_WAITCNT 0 - %sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM %sgpr4_sgpr5, 8, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`) - %sgpr6 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`) - %sgpr2_sgpr3 = S_LOAD_DWORDX2_IMM %sgpr4_sgpr5, 24, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`) - %sgpr7 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 16, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`) - %sgpr8 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 32, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`) + $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr4_sgpr5, 8, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`) + $sgpr6 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`) + $sgpr2_sgpr3 = S_LOAD_DWORDX2_IMM $sgpr4_sgpr5, 24, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`) + $sgpr7 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 16, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`) + $sgpr8 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 32, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`) S_WAITCNT 127 - %vgpr0 = V_MOV_B32_e32 %sgpr0, implicit %exec, implicit-def %vgpr0_vgpr1, implicit %sgpr0_sgpr1 - %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr4_sgpr5, 40, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`) - %vgpr1 = V_MOV_B32_e32 killed %sgpr1, implicit %exec, implicit killed %sgpr0_sgpr1, implicit %sgpr0_sgpr1, implicit %exec - %vgpr2 = V_MOV_B32_e32 killed %sgpr6, implicit %exec, implicit %exec - FLAT_STORE_DWORD killed %vgpr0_vgpr1, killed %vgpr2, 0, -1, 0, implicit %exec, implicit %flat_scr :: (volatile non-temporal store syncscope("agent") seq_cst 4 into %ir.agent_out) + $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 + $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr4_sgpr5, 40, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`) + $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit killed $sgpr0_sgpr1, implicit $sgpr0_sgpr1, implicit $exec + $vgpr2 = V_MOV_B32_e32 killed $sgpr6, implicit $exec, implicit $exec + FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("agent") seq_cst 4 into %ir.agent_out) S_WAITCNT 112 - %vgpr0 = V_MOV_B32_e32 %sgpr2, implicit %exec, implicit-def %vgpr0_vgpr1, implicit %sgpr2_sgpr3 - %vgpr1 = V_MOV_B32_e32 killed %sgpr3, implicit %exec, implicit killed %sgpr2_sgpr3, implicit %sgpr2_sgpr3, implicit %exec - %vgpr2 = V_MOV_B32_e32 killed %sgpr7, implicit %exec, implicit %exec - FLAT_STORE_DWORD killed %vgpr0_vgpr1, killed %vgpr2, 0, -1, 0, implicit %exec, implicit %flat_scr :: (volatile non-temporal store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out) + $vgpr0 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr2_sgpr3 + $vgpr1 = V_MOV_B32_e32 killed $sgpr3, implicit $exec, implicit killed $sgpr2_sgpr3, implicit $sgpr2_sgpr3, implicit $exec + $vgpr2 = V_MOV_B32_e32 killed $sgpr7, implicit $exec, implicit $exec + FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out) S_WAITCNT 112 - %vgpr0 = V_MOV_B32_e32 %sgpr4, implicit %exec, implicit-def %vgpr0_vgpr1, implicit %sgpr4_sgpr5 - %vgpr1 = V_MOV_B32_e32 killed %sgpr5, implicit %exec, implicit killed %sgpr4_sgpr5, implicit %sgpr4_sgpr5, implicit %exec - %vgpr2 = V_MOV_B32_e32 killed %sgpr8, implicit %exec, implicit %exec - FLAT_STORE_DWORD killed %vgpr0_vgpr1, killed %vgpr2, 0, -1, 0, implicit %exec, implicit %flat_scr :: (volatile non-temporal store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out) + $vgpr0 = V_MOV_B32_e32 $sgpr4, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr4_sgpr5 + $vgpr1 = V_MOV_B32_e32 killed $sgpr5, implicit $exec, implicit killed $sgpr4_sgpr5, implicit $sgpr4_sgpr5, implicit $exec + $vgpr2 = V_MOV_B32_e32 killed $sgpr8, implicit $exec, implicit $exec + FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out) S_ENDPGM ... diff --git a/llvm/test/CodeGen/MIR/AMDGPU/target-flags.mir b/llvm/test/CodeGen/MIR/AMDGPU/target-flags.mir index e69a94b59ea..569a9cf80d0 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/target-flags.mir +++ b/llvm/test/CodeGen/MIR/AMDGPU/target-flags.mir @@ -12,7 +12,7 @@ name: flags liveins: - - { reg: '%sgpr0_sgpr1' } + - { reg: '$sgpr0_sgpr1' } frameInfo: maxAlignment: 8 registers: @@ -20,12 +20,12 @@ registers: - { id: 1, class: sreg_64, preferred-register: '' } body: | bb.0: - liveins: %sgpr0_sgpr1 + liveins: $sgpr0_sgpr1 ; CHECK-LABEL: name: flags - ; CHECK: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead %scc + ; CHECK: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead $scc ; CHECK: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo ; CHECK: S_ENDPGM - %0 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead %scc + %0 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead $scc %1 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo S_ENDPGM diff --git a/llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir b/llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir index 32669de15ea..0f482bc8d8a 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir +++ b/llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir @@ -28,60 +28,60 @@ --- name: float liveins: - - { reg: '%sgpr0_sgpr1' } + - { reg: '$sgpr0_sgpr1' } frameInfo: maxAlignment: 8 body: | bb.0.entry: - liveins: %sgpr0_sgpr1 + liveins: $sgpr0_sgpr1 - %sgpr2_sgpr3 = S_GETPC_B64 - ; CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc - %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc - %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc - %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc - %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11, 0 - %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc - %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc - %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc - %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc - %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc - %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc - %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0, 0 - %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9, 0 - %sgpr7 = S_MOV_B32 61440 - %sgpr6 = S_MOV_B32 -1 - %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec - BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec + $sgpr2_sgpr3 = S_GETPC_B64 + ; CHECK: $sgpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start), implicit-def $scc, implicit-def $scc + $sgpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start), implicit-def $scc, implicit-def $scc + $sgpr3 = S_ADDC_U32 $sgpr3, 0, implicit-def $scc, implicit $scc, implicit-def $scc, implicit $scc + $sgpr4_sgpr5 = S_LSHR_B64 $sgpr2_sgpr3, 32, implicit-def dead $scc + $sgpr6 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 11, 0 + $sgpr7 = S_ASHR_I32 $sgpr6, 31, implicit-def dead $scc + $sgpr6_sgpr7 = S_LSHL_B64 $sgpr6_sgpr7, 2, implicit-def dead $scc + $sgpr2 = S_ADD_U32 $sgpr2, @float_gv, implicit-def $scc + $sgpr3 = S_ADDC_U32 $sgpr4, 0, implicit-def dead $scc, implicit $scc + $sgpr4 = S_ADD_U32 $sgpr2, $sgpr6, implicit-def $scc + $sgpr5 = S_ADDC_U32 $sgpr3, $sgpr7, implicit-def dead $scc, implicit $scc + $sgpr2 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 0, 0 + $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 9, 0 + $sgpr7 = S_MOV_B32 61440 + $sgpr6 = S_MOV_B32 -1 + $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec + BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec S_ENDPGM ... --- name: float2 liveins: - - { reg: '%sgpr0_sgpr1' } + - { reg: '$sgpr0_sgpr1' } frameInfo: maxAlignment: 8 body: | bb.0.entry: - liveins: %sgpr0_sgpr1 + liveins: $sgpr0_sgpr1 - %sgpr2_sgpr3 = S_GETPC_B64 - ; CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc - %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc - %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc - %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc - %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11, 0 - %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc - %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc - %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc - %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc - %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc - %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc - %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0, 0 - %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9, 0 - %sgpr7 = S_MOV_B32 61440 - %sgpr6 = S_MOV_B32 -1 - %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec - BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec + $sgpr2_sgpr3 = S_GETPC_B64 + ; CHECK: $sgpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def $scc, implicit-def $scc + $sgpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def $scc, implicit-def $scc + $sgpr3 = S_ADDC_U32 $sgpr3, 0, implicit-def $scc, implicit $scc, implicit-def $scc, implicit $scc + $sgpr4_sgpr5 = S_LSHR_B64 $sgpr2_sgpr3, 32, implicit-def dead $scc + $sgpr6 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 11, 0 + $sgpr7 = S_ASHR_I32 $sgpr6, 31, implicit-def dead $scc + $sgpr6_sgpr7 = S_LSHL_B64 $sgpr6_sgpr7, 2, implicit-def dead $scc + $sgpr2 = S_ADD_U32 $sgpr2, @float_gv, implicit-def $scc + $sgpr3 = S_ADDC_U32 $sgpr4, 0, implicit-def dead $scc, implicit $scc + $sgpr4 = S_ADD_U32 $sgpr2, $sgpr6, implicit-def $scc + $sgpr5 = S_ADDC_U32 $sgpr3, $sgpr7, implicit-def dead $scc, implicit $scc + $sgpr2 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 0, 0 + $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 9, 0 + $sgpr7 = S_MOV_B32 61440 + $sgpr6 = S_MOV_B32 -1 + $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec + BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec S_ENDPGM ... diff --git a/llvm/test/CodeGen/MIR/ARM/bundled-instructions.mir b/llvm/test/CodeGen/MIR/ARM/bundled-instructions.mir index 462d45c90b5..7d9d3f89f6a 100644 --- a/llvm/test/CodeGen/MIR/ARM/bundled-instructions.mir +++ b/llvm/test/CodeGen/MIR/ARM/bundled-instructions.mir @@ -23,53 +23,53 @@ name: test1 tracksRegLiveness: true liveins: - - { reg: '%r0' } + - { reg: '$r0' } body: | bb.0.entry: - liveins: %r0 + liveins: $r0 ; CHECK-LABEL: name: test1 - ; CHECK: %r1 = t2MOVi 0, 14, %noreg, %noreg - ; CHECK-NEXT: t2CMNri killed %r0, 78, 14, %noreg, implicit-def %cpsr - ; CHECK-NEXT: BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr { - ; CHECK-NEXT: t2IT 12, 8, implicit-def %itstate - ; CHECK-NEXT: %r1 = t2MOVi 1, 12, killed %cpsr, %noreg, implicit internal killed %itstate + ; CHECK: $r1 = t2MOVi 0, 14, $noreg, $noreg + ; CHECK-NEXT: t2CMNri killed $r0, 78, 14, $noreg, implicit-def $cpsr + ; CHECK-NEXT: BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr { + ; CHECK-NEXT: t2IT 12, 8, implicit-def $itstate + ; CHECK-NEXT: $r1 = t2MOVi 1, 12, killed $cpsr, $noreg, implicit internal killed $itstate ; CHECK-NEXT: } - ; CHECK-NEXT: %r0 = tMOVr killed %r1, 14, %noreg - ; CHECK-NEXT: tBX_RET 14, %noreg, implicit killed %r0 - %r1 = t2MOVi 0, 14, _, _ - t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr - BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr { - t2IT 12, 8, implicit-def %itstate - %r1 = t2MOVi 1, 12, killed %cpsr, _, implicit internal killed %itstate + ; CHECK-NEXT: $r0 = tMOVr killed $r1, 14, $noreg + ; CHECK-NEXT: tBX_RET 14, $noreg, implicit killed $r0 + $r1 = t2MOVi 0, 14, _, _ + t2CMNri killed $r0, 78, 14, _, implicit-def $cpsr + BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr { + t2IT 12, 8, implicit-def $itstate + $r1 = t2MOVi 1, 12, killed $cpsr, _, implicit internal killed $itstate } - %r0 = tMOVr killed %r1, 14, _ - tBX_RET 14, _, implicit killed %r0 + $r0 = tMOVr killed $r1, 14, _ + tBX_RET 14, _, implicit killed $r0 ... --- name: test2 tracksRegLiveness: true liveins: - - { reg: '%r0' } + - { reg: '$r0' } body: | bb.0.entry: - liveins: %r0 + liveins: $r0 ; Verify that the next machine instruction can be on the same line as ; '{' or '}'. ; CHECK-LABEL: name: test2 - ; CHECK: %r1 = t2MOVi 0, 14, %noreg, %noreg - ; CHECK-NEXT: t2CMNri killed %r0, 78, 14, %noreg, implicit-def %cpsr - ; CHECK-NEXT: BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr { - ; CHECK-NEXT: t2IT 12, 8, implicit-def %itstate - ; CHECK-NEXT: %r1 = t2MOVi 1, 12, killed %cpsr, %noreg, implicit internal killed %itstate + ; CHECK: $r1 = t2MOVi 0, 14, $noreg, $noreg + ; CHECK-NEXT: t2CMNri killed $r0, 78, 14, $noreg, implicit-def $cpsr + ; CHECK-NEXT: BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr { + ; CHECK-NEXT: t2IT 12, 8, implicit-def $itstate + ; CHECK-NEXT: $r1 = t2MOVi 1, 12, killed $cpsr, $noreg, implicit internal killed $itstate ; CHECK-NEXT: } - ; CHECK-NEXT: %r0 = tMOVr killed %r1, 14, %noreg - ; CHECK-NEXT: tBX_RET 14, %noreg, implicit killed %r0 - %r1 = t2MOVi 0, 14, _, _ - t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr - BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr { t2IT 12, 8, implicit-def %itstate - %r1 = t2MOVi 1, 12, killed %cpsr, _, internal implicit killed %itstate - } %r0 = tMOVr killed %r1, 14, _ - tBX_RET 14, _, implicit killed %r0 + ; CHECK-NEXT: $r0 = tMOVr killed $r1, 14, $noreg + ; CHECK-NEXT: tBX_RET 14, $noreg, implicit killed $r0 + $r1 = t2MOVi 0, 14, _, _ + t2CMNri killed $r0, 78, 14, _, implicit-def $cpsr + BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr { t2IT 12, 8, implicit-def $itstate + $r1 = t2MOVi 1, 12, killed $cpsr, _, internal implicit killed $itstate + } $r0 = tMOVr killed $r1, 14, _ + tBX_RET 14, _, implicit killed $r0 ... diff --git a/llvm/test/CodeGen/MIR/ARM/cfi-same-value.mir b/llvm/test/CodeGen/MIR/ARM/cfi-same-value.mir index cba3ef2063b..e007f45efb9 100644 --- a/llvm/test/CodeGen/MIR/ARM/cfi-same-value.mir +++ b/llvm/test/CodeGen/MIR/ARM/cfi-same-value.mir @@ -23,58 +23,58 @@ frameInfo: stack: - { id: 0, name: mem, offset: -48, size: 40, alignment: 4 } - { id: 1, type: spill-slot, offset: -4, size: 4, alignment: 4, - callee-saved-register: '%lr' } + callee-saved-register: '$lr' } - { id: 2, type: spill-slot, offset: -8, size: 4, alignment: 4, - callee-saved-register: '%r11' } + callee-saved-register: '$r11' } body: | bb.0: successors: %bb.2, %bb.1 - liveins: %r11, %lr + liveins: $r11, $lr - %sp = STMDB_UPD %sp, 14, _, %r4, %r5 + $sp = STMDB_UPD $sp, 14, _, $r4, $r5 CFI_INSTRUCTION def_cfa_offset 8 - CFI_INSTRUCTION offset %r5, -4 - CFI_INSTRUCTION offset %r4, -8 - %r5 = MOVr %sp, 14, _, _ - %r4 = MRC 15, 0, 13, 0, 3, 14, _ - %r4 = LDRi12 %r4, 4, 14, _ - CMPrr %r4, %r5, 14, _, implicit-def %cpsr - Bcc %bb.2, 3, %cpsr + CFI_INSTRUCTION offset $r5, -4 + CFI_INSTRUCTION offset $r4, -8 + $r5 = MOVr $sp, 14, _, _ + $r4 = MRC 15, 0, 13, 0, 3, 14, _ + $r4 = LDRi12 $r4, 4, 14, _ + CMPrr $r4, $r5, 14, _, implicit-def $cpsr + Bcc %bb.2, 3, $cpsr bb.1: successors: %bb.2 - liveins: %r11, %lr + liveins: $r11, $lr - %r4 = MOVi 48, 14, _, _ - %r5 = MOVi 0, 14, _, _ - %sp = STMDB_UPD %sp, 14, _, %lr + $r4 = MOVi 48, 14, _, _ + $r5 = MOVi 0, 14, _, _ + $sp = STMDB_UPD $sp, 14, _, $lr CFI_INSTRUCTION def_cfa_offset 12 - CFI_INSTRUCTION offset %lr, -12 - BL &__morestack, implicit-def %lr, implicit %sp - %sp = LDMIA_UPD %sp, 14, _, %lr - %sp = LDMIA_UPD %sp, 14, _, %r4, %r5 + CFI_INSTRUCTION offset $lr, -12 + BL &__morestack, implicit-def $lr, implicit $sp + $sp = LDMIA_UPD $sp, 14, _, $lr + $sp = LDMIA_UPD $sp, 14, _, $r4, $r5 CFI_INSTRUCTION def_cfa_offset 0 BX_RET 14, _ bb.2: - liveins: %r11, %lr + liveins: $r11, $lr - %sp = LDMIA_UPD %sp, 14, _, %r4, %r5 + $sp = LDMIA_UPD $sp, 14, _, $r4, $r5 CFI_INSTRUCTION def_cfa_offset 0 - ; CHECK: CFI_INSTRUCTION same_value %r4 - ; CHECK-NEXT: CFI_INSTRUCTION same_value %r5 - CFI_INSTRUCTION same_value %r4 - CFI_INSTRUCTION same_value %r5 - %sp = frame-setup STMDB_UPD %sp, 14, _, killed %r11, killed %lr + ; CHECK: CFI_INSTRUCTION same_value $r4 + ; CHECK-NEXT: CFI_INSTRUCTION same_value $r5 + CFI_INSTRUCTION same_value $r4 + CFI_INSTRUCTION same_value $r5 + $sp = frame-setup STMDB_UPD $sp, 14, _, killed $r11, killed $lr frame-setup CFI_INSTRUCTION def_cfa_offset 8 - frame-setup CFI_INSTRUCTION offset %lr, -4 - frame-setup CFI_INSTRUCTION offset %r11, -8 - %sp = frame-setup SUBri killed %sp, 40, 14, _, _ + frame-setup CFI_INSTRUCTION offset $lr, -4 + frame-setup CFI_INSTRUCTION offset $r11, -8 + $sp = frame-setup SUBri killed $sp, 40, 14, _, _ frame-setup CFI_INSTRUCTION def_cfa_offset 48 - %r0 = MOVr %sp, 14, _, _ - %r1 = MOVi 10, 14, _, _ - BL @dummy_use, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit killed %r1, implicit-def %sp - %sp = ADDri killed %sp, 40, 14, _, _ - %sp = LDMIA_UPD %sp, 14, _, %r4, %r5 + $r0 = MOVr $sp, 14, _, _ + $r1 = MOVi 10, 14, _, _ + BL @dummy_use, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit killed $r1, implicit-def $sp + $sp = ADDri killed $sp, 40, 14, _, _ + $sp = LDMIA_UPD $sp, 14, _, $r4, $r5 MOVPCLR 14, _ ... diff --git a/llvm/test/CodeGen/MIR/ARM/expected-closing-brace.mir b/llvm/test/CodeGen/MIR/ARM/expected-closing-brace.mir index 4304935067a..c7bc1c13a4c 100644 --- a/llvm/test/CodeGen/MIR/ARM/expected-closing-brace.mir +++ b/llvm/test/CodeGen/MIR/ARM/expected-closing-brace.mir @@ -25,26 +25,26 @@ name: test1 tracksRegLiveness: true liveins: - - { reg: '%r0' } + - { reg: '$r0' } body: | bb.0.entry: successors: %bb.1.foo - liveins: %r0 + liveins: $r0 bb.1.foo: successors: %bb.2.if.then, %bb.1.foo - liveins: %r0 + liveins: $r0 - t2CMNri %r0, 78, 14, _, implicit-def %cpsr - %r1 = t2MOVi 0, 14, _, _ - BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr { - t2IT 12, 8, implicit-def %itstate - %r1 = t2MOVi 1, 12, killed %cpsr, _, implicit killed %itstate - t2CMNri %r0, 77, 14, _, implicit-def %cpsr - t2Bcc %bb.1.foo, 11, killed %cpsr + t2CMNri $r0, 78, 14, _, implicit-def $cpsr + $r1 = t2MOVi 0, 14, _, _ + BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr { + t2IT 12, 8, implicit-def $itstate + $r1 = t2MOVi 1, 12, killed $cpsr, _, implicit killed $itstate + t2CMNri $r0, 77, 14, _, implicit-def $cpsr + t2Bcc %bb.1.foo, 11, killed $cpsr ; CHECK: [[@LINE+1]]:3: expected '}' bb.2.if.then: - liveins: %r1 + liveins: $r1 - %r0 = tMOVr killed %r1, 14, _ - tBX_RET 14, _, implicit killed %r0 + $r0 = tMOVr killed $r1, 14, _ + tBX_RET 14, _, implicit killed $r0 ... diff --git a/llvm/test/CodeGen/MIR/ARM/extraneous-closing-brace-error.mir b/llvm/test/CodeGen/MIR/ARM/extraneous-closing-brace-error.mir index fcd938efbb9..02b06bc3432 100644 --- a/llvm/test/CodeGen/MIR/ARM/extraneous-closing-brace-error.mir +++ b/llvm/test/CodeGen/MIR/ARM/extraneous-closing-brace-error.mir @@ -10,11 +10,11 @@ name: test1 tracksRegLiveness: true liveins: - - { reg: '%r0' } + - { reg: '$r0' } body: | bb.0.entry: - liveins: %r0 - tBX_RET 14, _, implicit killed %r0 + liveins: $r0 + tBX_RET 14, _, implicit killed $r0 ; CHECK: [[@LINE+1]]:5: extraneous closing brace ('}') } ... diff --git a/llvm/test/CodeGen/MIR/ARM/nested-instruction-bundle-error.mir b/llvm/test/CodeGen/MIR/ARM/nested-instruction-bundle-error.mir index 63b997046d0..f05af43127d 100644 --- a/llvm/test/CodeGen/MIR/ARM/nested-instruction-bundle-error.mir +++ b/llvm/test/CodeGen/MIR/ARM/nested-instruction-bundle-error.mir @@ -12,19 +12,19 @@ name: test1 tracksRegLiveness: true liveins: - - { reg: '%r0' } + - { reg: '$r0' } body: | bb.0.entry: - liveins: %r0 - %r1 = t2MOVi 0, 14, _, _ - t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr - BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr { - t2IT 12, 8, implicit-def %itstate - %r1 = t2MOVi 1, 12, killed %cpsr, _ + liveins: $r0 + $r1 = t2MOVi 0, 14, _, _ + t2CMNri killed $r0, 78, 14, _, implicit-def $cpsr + BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr { + t2IT 12, 8, implicit-def $itstate + $r1 = t2MOVi 1, 12, killed $cpsr, _ ; CHECK: [[@LINE+1]]:14: nested instruction bundles are not allowed BUNDLE { } } - %r0 = tMOVr killed %r1, 14, _ - tBX_RET 14, _, implicit killed %r0 + $r0 = tMOVr killed $r1, 14, _ + tBX_RET 14, _, implicit killed $r0 ... diff --git a/llvm/test/CodeGen/MIR/Hexagon/parse-lane-masks.mir b/llvm/test/CodeGen/MIR/Hexagon/parse-lane-masks.mir index 7f6f3469478..1b6dc3b4c41 100644 --- a/llvm/test/CodeGen/MIR/Hexagon/parse-lane-masks.mir +++ b/llvm/test/CodeGen/MIR/Hexagon/parse-lane-masks.mir @@ -3,7 +3,7 @@ # CHECK-LABEL: name: foo # CHECK: bb.0: -# CHECK: liveins: %d0:0x00000002, %d1, %d2:0x00000010 +# CHECK: liveins: $d0:0x00000002, $d1, $d2:0x00000010 --- | define void @foo() { @@ -17,7 +17,7 @@ tracksRegLiveness: true body: | bb.0: - liveins: %d0:0x00002, %d1, %d2:16 + liveins: $d0:0x00002, $d1, $d2:16 A2_nop ... diff --git a/llvm/test/CodeGen/MIR/Hexagon/target-flags.mir b/llvm/test/CodeGen/MIR/Hexagon/target-flags.mir index 656e0a6ea85..a4ea8821eb6 100644 --- a/llvm/test/CodeGen/MIR/Hexagon/target-flags.mir +++ b/llvm/test/CodeGen/MIR/Hexagon/target-flags.mir @@ -6,31 +6,31 @@ body: | bb.0: ; CHECK: target-flags(hexagon-pcrel) - %r0 = A2_tfrsi target-flags (hexagon-pcrel) 0 + $r0 = A2_tfrsi target-flags (hexagon-pcrel) 0 ; CHECK: target-flags(hexagon-got) - %r0 = A2_tfrsi target-flags (hexagon-got) 0 + $r0 = A2_tfrsi target-flags (hexagon-got) 0 ; CHECK: target-flags(hexagon-lo16) - %r0 = A2_tfrsi target-flags (hexagon-lo16) 0 + $r0 = A2_tfrsi target-flags (hexagon-lo16) 0 ; CHECK: target-flags(hexagon-hi16) - %r0 = A2_tfrsi target-flags (hexagon-hi16) 0 + $r0 = A2_tfrsi target-flags (hexagon-hi16) 0 ; CHECK: target-flags(hexagon-gprel) - %r0 = A2_tfrsi target-flags (hexagon-gprel) 0 + $r0 = A2_tfrsi target-flags (hexagon-gprel) 0 ; CHECK: target-flags(hexagon-gdgot) - %r0 = A2_tfrsi target-flags (hexagon-gdgot) 0 + $r0 = A2_tfrsi target-flags (hexagon-gdgot) 0 ; CHECK: target-flags(hexagon-gdplt) - %r0 = A2_tfrsi target-flags (hexagon-gdplt) 0 + $r0 = A2_tfrsi target-flags (hexagon-gdplt) 0 ; CHECK: target-flags(hexagon-ie) - %r0 = A2_tfrsi target-flags (hexagon-ie) 0 + $r0 = A2_tfrsi target-flags (hexagon-ie) 0 ; CHECK: target-flags(hexagon-iegot) - %r0 = A2_tfrsi target-flags (hexagon-iegot) 0 + $r0 = A2_tfrsi target-flags (hexagon-iegot) 0 ; CHECK: target-flags(hexagon-tprel) - %r0 = A2_tfrsi target-flags (hexagon-tprel) 0 + $r0 = A2_tfrsi target-flags (hexagon-tprel) 0 ; CHECK: target-flags(hexagon-ext) - %r0 = A2_tfrsi target-flags (hexagon-ext) 0 + $r0 = A2_tfrsi target-flags (hexagon-ext) 0 ; CHECK: target-flags(hexagon-pcrel, hexagon-ext) - %r0 = A2_tfrsi target-flags (hexagon-pcrel,hexagon-ext) 0 + $r0 = A2_tfrsi target-flags (hexagon-pcrel,hexagon-ext) 0 ; CHECK: target-flags(hexagon-ie, hexagon-ext) - %r0 = A2_tfrsi target-flags (hexagon-ie,hexagon-ext) 0 + $r0 = A2_tfrsi target-flags (hexagon-ie,hexagon-ext) 0 ... diff --git a/llvm/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir b/llvm/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir index 33a4136ceb8..002b60be8b8 100644 --- a/llvm/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir +++ b/llvm/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir @@ -12,7 +12,7 @@ name: test tracksRegLiveness: true liveins: - - { reg: '%a0' } + - { reg: '$a0' } frameInfo: stackSize: 24 maxAlignment: 4 @@ -21,21 +21,21 @@ frameInfo: maxCallFrameSize: 16 stack: - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, - callee-saved-register: '%ra' } + callee-saved-register: '$ra' } body: | bb.0.entry: - liveins: %a0, %ra + liveins: $a0, $ra - Save16 %ra, 24, implicit-def %sp, implicit %sp - %v0, %v1 = GotPrologue16 &_gp_disp, &_gp_disp - %v0 = SllX16 killed %v0, 16 - %v0 = AdduRxRyRz16 killed %v1, killed %v0 + Save16 $ra, 24, implicit-def $sp, implicit $sp + $v0, $v1 = GotPrologue16 &_gp_disp, &_gp_disp + $v0 = SllX16 killed $v0, 16 + $v0 = AdduRxRyRz16 killed $v1, killed $v0 ; CHECK: [[@LINE+1]]:67: expected a global value or an external symbol after 'call-entry' - %v1 = LwRxRyOffMemX16 %v0, @foo, 0 :: (load 4 from call-entry foo) - %t9 = COPY %v1 - %gp = COPY killed %v0 - JumpLinkReg16 killed %v1, csr_o32, implicit-def %ra, implicit killed %t9, implicit %a0, implicit killed %gp, implicit-def %sp, implicit-def dead %v0 - %v0 = LiRxImmX16 0 - %ra = Restore16 24, implicit-def %sp, implicit %sp - RetRA16 implicit %v0 + $v1 = LwRxRyOffMemX16 $v0, @foo, 0 :: (load 4 from call-entry foo) + $t9 = COPY $v1 + $gp = COPY killed $v0 + JumpLinkReg16 killed $v1, csr_o32, implicit-def $ra, implicit killed $t9, implicit $a0, implicit killed $gp, implicit-def $sp, implicit-def dead $v0 + $v0 = LiRxImmX16 0 + $ra = Restore16 24, implicit-def $sp, implicit $sp + RetRA16 implicit $v0 ... diff --git a/llvm/test/CodeGen/MIR/Mips/memory-operands.mir b/llvm/test/CodeGen/MIR/Mips/memory-operands.mir index 62cddcf5588..f3a813612ca 100644 --- a/llvm/test/CodeGen/MIR/Mips/memory-operands.mir +++ b/llvm/test/CodeGen/MIR/Mips/memory-operands.mir @@ -29,7 +29,7 @@ name: test tracksRegLiveness: true liveins: - - { reg: '%a0' } + - { reg: '$a0' } frameInfo: stackSize: 24 maxAlignment: 4 @@ -38,26 +38,26 @@ frameInfo: maxCallFrameSize: 16 stack: - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, - callee-saved-register: '%ra' } + callee-saved-register: '$ra' } body: | bb.0.entry: - liveins: %a0, %ra + liveins: $a0, $ra - Save16 %ra, 24, implicit-def %sp, implicit %sp + Save16 $ra, 24, implicit-def $sp, implicit $sp CFI_INSTRUCTION def_cfa_offset 24 - CFI_INSTRUCTION offset %ra_64, -4 - %v0, %v1 = GotPrologue16 &_gp_disp, &_gp_disp - %v0 = SllX16 killed %v0, 16 - %v0 = AdduRxRyRz16 killed %v1, killed %v0 + CFI_INSTRUCTION offset $ra_64, -4 + $v0, $v1 = GotPrologue16 &_gp_disp, &_gp_disp + $v0 = SllX16 killed $v0, 16 + $v0 = AdduRxRyRz16 killed $v1, killed $v0 ; CHECK-LABEL: name: test - ; CHECK: %v1 = LwRxRyOffMemX16 %v0, @foo :: (load 4 from call-entry @foo) - %v1 = LwRxRyOffMemX16 %v0, @foo :: (load 4 from call-entry @foo) - %t9 = COPY %v1 - %gp = COPY killed %v0 - JumpLinkReg16 killed %v1, csr_o32, implicit-def %ra, implicit killed %t9, implicit %a0, implicit killed %gp, implicit-def %sp, implicit-def dead %v0 - %v0 = LiRxImmX16 0 - %ra = Restore16 24, implicit-def %sp, implicit %sp - RetRA16 implicit %v0 + ; CHECK: $v1 = LwRxRyOffMemX16 $v0, @foo :: (load 4 from call-entry @foo) + $v1 = LwRxRyOffMemX16 $v0, @foo :: (load 4 from call-entry @foo) + $t9 = COPY $v1 + $gp = COPY killed $v0 + JumpLinkReg16 killed $v1, csr_o32, implicit-def $ra, implicit killed $t9, implicit $a0, implicit killed $gp, implicit-def $sp, implicit-def dead $v0 + $v0 = LiRxImmX16 0 + $ra = Restore16 24, implicit-def $sp, implicit $sp + RetRA16 implicit $v0 ... --- name: test2 @@ -70,33 +70,33 @@ frameInfo: maxCallFrameSize: 16 stack: - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, - callee-saved-register: '%ra' } + callee-saved-register: '$ra' } - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, - callee-saved-register: '%s2' } + callee-saved-register: '$s2' } - { id: 2, type: spill-slot, offset: -12, size: 4, alignment: 4, - callee-saved-register: '%s0' } + callee-saved-register: '$s0' } body: | bb.0.entry: - liveins: %ra, %s2, %s0, %ra, %s2, %s0 + liveins: $ra, $s2, $s0, $ra, $s2, $s0 - SaveX16 %s0, %ra, %s2, 32, implicit-def %sp, implicit %sp + SaveX16 $s0, $ra, $s2, 32, implicit-def $sp, implicit $sp CFI_INSTRUCTION def_cfa_offset 32 - CFI_INSTRUCTION offset %ra_64, -4 - CFI_INSTRUCTION offset %s2_64, -8 - CFI_INSTRUCTION offset %s0_64, -12 - %v0, %v1 = GotPrologue16 &_gp_disp, &_gp_disp - %v0 = SllX16 killed %v0, 16 - %s0 = AdduRxRyRz16 killed %v1, killed %v0 - %v0 = LwRxRyOffMemX16 %s0, @g :: (load 4 from call-entry @g) + CFI_INSTRUCTION offset $ra_64, -4 + CFI_INSTRUCTION offset $s2_64, -8 + CFI_INSTRUCTION offset $s0_64, -12 + $v0, $v1 = GotPrologue16 &_gp_disp, &_gp_disp + $v0 = SllX16 killed $v0, 16 + $s0 = AdduRxRyRz16 killed $v1, killed $v0 + $v0 = LwRxRyOffMemX16 $s0, @g :: (load 4 from call-entry @g) ; CHECK-LABEL: test2 - ; CHECK: %v1 = LwRxRyOffMemX16 %s0, &__mips16_call_stub_sf_0 :: (load 4 from call-entry &__mips16_call_stub_sf_0) - %v1 = LwRxRyOffMemX16 %s0, &__mips16_call_stub_sf_0 :: (load 4 from call-entry &__mips16_call_stub_sf_0) - %gp = COPY %s0 - JumpLinkReg16 killed %v1, csr_o32, implicit-def %ra, implicit %v0, implicit killed %gp, implicit-def %sp, implicit-def %v0 - %v1 = LwRxRyOffMemX16 %s0, @__mips16_ret_sf :: (load 4 from call-entry @__mips16_ret_sf) - %t9 = COPY %v1 - %gp = COPY killed %s0 - JumpLinkReg16 killed %v1, csr_mips16rethelper, implicit-def %ra, implicit killed %t9, implicit %v0, implicit killed %gp, implicit-def %sp - %s0, %ra, %s2 = RestoreX16 32, implicit-def %sp, implicit %sp - RetRA16 implicit %v0 + ; CHECK: $v1 = LwRxRyOffMemX16 $s0, &__mips16_call_stub_sf_0 :: (load 4 from call-entry &__mips16_call_stub_sf_0) + $v1 = LwRxRyOffMemX16 $s0, &__mips16_call_stub_sf_0 :: (load 4 from call-entry &__mips16_call_stub_sf_0) + $gp = COPY $s0 + JumpLinkReg16 killed $v1, csr_o32, implicit-def $ra, implicit $v0, implicit killed $gp, implicit-def $sp, implicit-def $v0 + $v1 = LwRxRyOffMemX16 $s0, @__mips16_ret_sf :: (load 4 from call-entry @__mips16_ret_sf) + $t9 = COPY $v1 + $gp = COPY killed $s0 + JumpLinkReg16 killed $v1, csr_mips16rethelper, implicit-def $ra, implicit killed $t9, implicit $v0, implicit killed $gp, implicit-def $sp + $s0, $ra, $s2 = RestoreX16 32, implicit-def $sp, implicit $sp + RetRA16 implicit $v0 ... diff --git a/llvm/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir b/llvm/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir index d1c38acd5d3..b6cee56f2bb 100644 --- a/llvm/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir +++ b/llvm/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir @@ -28,17 +28,17 @@ registers: - { id: 3, class: gprc } - { id: 4, class: g8rc } liveins: - - { reg: '%x3', virtual-reg: '%0' } + - { reg: '$x3', virtual-reg: '%0' } body: | bb.0.entry: - liveins: %x3 + liveins: $x3 - %0 = COPY %x3 + %0 = COPY $x3 %1 = LWZ 0, %0 :: (load 4 from %ir.p) %2 = LI 0 %3 = RLWIMI %2, killed %1, 0, 0, 31 %4 = EXTSW_32_64 killed %3 - %x3 = COPY %4 - ; CHECK: BLR8 implicit %lr8, implicit %rm, implicit %x3 - BLR8 implicit %lr8, implicit %rm, implicit %x3 + $x3 = COPY %4 + ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit $x3 + BLR8 implicit $lr8, implicit $rm, implicit $x3 ... diff --git a/llvm/test/CodeGen/MIR/X86/auto-successor.mir b/llvm/test/CodeGen/MIR/X86/auto-successor.mir index 23b4f91b3b6..8d79577f271 100644 --- a/llvm/test/CodeGen/MIR/X86/auto-successor.mir +++ b/llvm/test/CodeGen/MIR/X86/auto-successor.mir @@ -4,31 +4,31 @@ # CHECK-LABEL: name: func0 # CHECK: bb.0: # CHECK-NOT: successors -# CHECK: JE_1 %bb.1, implicit undef %eflags +# CHECK: JE_1 %bb.1, implicit undef $eflags # CHECK: JMP_1 %bb.3 # CHECK: bb.1: # CHECK-NOT: successors # CHECK: bb.2: # CHECK-NOT: successors -# CHECK: JE_1 %bb.1, implicit undef %eflags +# CHECK: JE_1 %bb.1, implicit undef $eflags # CHECK: bb.3: -# CHECK: RETQ undef %eax +# CHECK: RETQ undef $eax name: func0 body: | bb.0: - JE_1 %bb.1, implicit undef %eflags + JE_1 %bb.1, implicit undef $eflags JMP_1 %bb.3 bb.1: bb.2: - JE_1 %bb.1, implicit undef %eflags + JE_1 %bb.1, implicit undef $eflags bb.3: - JE_1 %bb.4, implicit undef %eflags ; condjump+fallthrough to same block + JE_1 %bb.4, implicit undef $eflags ; condjump+fallthrough to same block bb.4: - RETQ undef %eax + RETQ undef $eax ... --- # Some cases that need explicit successors: @@ -39,23 +39,23 @@ body: | ; CHECK: bb.0: ; CHECK: successors: %bb.3, %bb.1 successors: %bb.3, %bb.1 ; different order than operands - JE_1 %bb.1, implicit undef %eflags + JE_1 %bb.1, implicit undef $eflags JMP_1 %bb.3 bb.1: ; CHECK: bb.1: ; CHECK: successors: %bb.2, %bb.1 successors: %bb.2, %bb.1 ; different order (fallthrough variant) - JE_1 %bb.1, implicit undef %eflags + JE_1 %bb.1, implicit undef $eflags bb.2: ; CHECK: bb.2: ; CHECK: successors: %bb.1(0x60000000), %bb.3(0x20000000) successors: %bb.1(3), %bb.3(1) ; branch probabilities not normalized - JE_1 %bb.1, implicit undef %eflags + JE_1 %bb.1, implicit undef $eflags bb.3: ; CHECK: bb.3: - ; CHECK: RETQ undef %eax - RETQ undef %eax + ; CHECK: RETQ undef $eax + RETQ undef $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir b/llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir index b347368a94b..7212dceb744 100644 --- a/llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir +++ b/llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir @@ -26,12 +26,12 @@ name: test tracksRegLiveness: true body: | ; CHECK-LABEL: bb.0.body: - ; CHECK-NEXT: liveins: %edi, %esi + ; CHECK-NEXT: liveins: $edi, $esi bb.0.body: - liveins: %edi, %esi + liveins: $edi, $esi - %eax = LEA64_32r killed %rdi, 1, killed %rsi, 0, _ - RETQ %eax + $eax = LEA64_32r killed $rdi, 1, killed $rsi, 0, _ + RETQ $eax ... --- name: test2 @@ -41,13 +41,13 @@ body: | ; Verify that we can have multiple lists of liveins that will be merged into ; one. ; CHECK: bb.0.body: - ; CHECK-NEXT: liveins: %edi, %esi + ; CHECK-NEXT: liveins: $edi, $esi bb.0.body: - liveins: %edi - liveins: %esi + liveins: $edi + liveins: $esi - %eax = LEA64_32r killed %rdi, 1, killed %rsi, 0, _ - RETQ %eax + $eax = LEA64_32r killed $rdi, 1, killed $rsi, 0, _ + RETQ $eax ... --- name: test3 @@ -56,10 +56,10 @@ body: | ; Verify that we can have an empty list of liveins. ; CHECK-LABEL: name: test3 ; CHECK: bb.0.body: - ; CHECK-NEXT: %eax = MOV32r0 implicit-def dead %eflags + ; CHECK-NEXT: $eax = MOV32r0 implicit-def dead $eflags bb.0.body: liveins: - %eax = MOV32r0 implicit-def dead %eflags - RETQ killed %eax + $eax = MOV32r0 implicit-def dead $eflags + RETQ killed $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir b/llvm/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir index 01c226a3453..cf7c57bd85d 100644 --- a/llvm/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir +++ b/llvm/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir @@ -19,23 +19,23 @@ name: foo tracksRegLiveness: true liveins: - - { reg: '%edi' } + - { reg: '$edi' } body: | bb.0.entry: successors: %bb.1.less, %bb.2.exit - liveins: %edi 44 + liveins: $edi 44 - CMP32ri8 %edi, 10, implicit-def %eflags - JG_1 %bb.2.exit, implicit killed %eflags + CMP32ri8 $edi, 10, implicit-def $eflags + JG_1 %bb.2.exit, implicit killed $eflags ; CHECK: [[@LINE+1]]:8: basic block definition should be located at the start of the line less bb.1: - %eax = MOV32r0 implicit-def dead %eflags - RETQ killed %eax + $eax = MOV32r0 implicit-def dead $eflags + RETQ killed $eax bb.2.exit: - liveins: %edi + liveins: $edi - %eax = COPY killed %edi - RETQ killed %eax + $eax = COPY killed $edi + RETQ killed $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/block-address-operands.mir b/llvm/test/CodeGen/MIR/X86/block-address-operands.mir index 85ce65275ce..4d72fe84c0b 100644 --- a/llvm/test/CodeGen/MIR/X86/block-address-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/block-address-operands.mir @@ -57,10 +57,10 @@ name: test body: | bb.0.entry: successors: %bb.1.block - ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test, %ir-block.block), %noreg - %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _ - MOV64mr %rip, 1, _, @addr, _, killed %rax - JMP64m %rip, 1, _, @addr, _ + ; CHECK: $rax = LEA64r $rip, 1, $noreg, blockaddress(@test, %ir-block.block), $noreg + $rax = LEA64r $rip, 1, _, blockaddress(@test, %ir-block.block), _ + MOV64mr $rip, 1, _, @addr, _, killed $rax + JMP64m $rip, 1, _, @addr, _ bb.1.block (address-taken): RETQ @@ -71,10 +71,10 @@ tracksRegLiveness: true body: | bb.0.entry: successors: %bb.1 - ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test2, %ir-block."quoted block"), %noreg - %rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _ - MOV64mr %rip, 1, _, @addr, _, killed %rax - JMP64m %rip, 1, _, @addr, _ + ; CHECK: $rax = LEA64r $rip, 1, $noreg, blockaddress(@test2, %ir-block."quoted block"), $noreg + $rax = LEA64r $rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _ + MOV64mr $rip, 1, _, @addr, _, killed $rax + JMP64m $rip, 1, _, @addr, _ bb.1 (address-taken): RETQ @@ -84,11 +84,11 @@ name: slot_in_other_function tracksRegLiveness: true body: | bb.0.entry: - liveins: %rdi + liveins: $rdi ; CHECK-LABEL: name: slot_in_other_function - ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test3, %ir-block.0), %noreg - %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _ - MOV64mr killed %rdi, 1, _, 0, _, killed %rax + ; CHECK: $rax = LEA64r $rip, 1, $noreg, blockaddress(@test3, %ir-block.0), $noreg + $rax = LEA64r $rip, 1, _, blockaddress(@test3, %ir-block.0), _ + MOV64mr killed $rdi, 1, _, 0, _, killed $rax RETQ ... --- @@ -98,10 +98,10 @@ body: | bb.0.entry: successors: %bb.1 ; CHECK-LABEL: name: test3 - ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test3, %ir-block.0), %noreg - %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _ - MOV64mr %rip, 1, _, @addr, _, killed %rax - JMP64m %rip, 1, _, @addr, _ + ; CHECK: $rax = LEA64r $rip, 1, $noreg, blockaddress(@test3, %ir-block.0), $noreg + $rax = LEA64r $rip, 1, _, blockaddress(@test3, %ir-block.0), _ + MOV64mr $rip, 1, _, @addr, _, killed $rax + JMP64m $rip, 1, _, @addr, _ bb.1 (address-taken): RETQ @@ -111,10 +111,10 @@ name: test4 body: | bb.0.entry: successors: %bb.1.block - ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test, %ir-block.block) + 2, %noreg - %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _ - MOV64mr %rip, 1, _, @addr, _, killed %rax - JMP64m %rip, 1, _, @addr, _ + ; CHECK: $rax = LEA64r $rip, 1, $noreg, blockaddress(@test, %ir-block.block) + 2, $noreg + $rax = LEA64r $rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _ + MOV64mr $rip, 1, _, @addr, _, killed $rax + JMP64m $rip, 1, _, @addr, _ bb.1.block (address-taken): RETQ diff --git a/llvm/test/CodeGen/MIR/X86/branch-probabilities.mir b/llvm/test/CodeGen/MIR/X86/branch-probabilities.mir index 4aacd2d5cef..8f3ca9da646 100644 --- a/llvm/test/CodeGen/MIR/X86/branch-probabilities.mir +++ b/llvm/test/CodeGen/MIR/X86/branch-probabilities.mir @@ -8,11 +8,11 @@ name: test body: | bb.0: successors: %bb.1(4), %bb.2(1) - JE_1 %bb.2, implicit undef %eflags + JE_1 %bb.2, implicit undef $eflags bb.1: NOOP bb.2: - RETQ undef %eax + RETQ undef $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/callee-saved-info.mir b/llvm/test/CodeGen/MIR/X86/callee-saved-info.mir index 886465148ae..98c1e3a8b30 100644 --- a/llvm/test/CodeGen/MIR/X86/callee-saved-info.mir +++ b/llvm/test/CodeGen/MIR/X86/callee-saved-info.mir @@ -36,10 +36,10 @@ name: compute tracksRegLiveness: true body: | bb.0.body: - liveins: %edi + liveins: $edi - %eax = COPY killed %edi - RETQ killed %eax + $eax = COPY killed $edi + RETQ killed $eax ... --- name: func @@ -50,47 +50,47 @@ frameInfo: adjustsStack: true hasCalls: true # CHECK: fixedStack: -# CHECK: callee-saved-register: '%rbx', callee-saved-restored: true } +# CHECK: callee-saved-register: '$rbx', callee-saved-restored: true } fixedStack: - - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%rbx' } + - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '$rbx' } # CHECK: stack: # CHECK-NEXT: - { id: 0 -# CHECK: callee-saved-register: '%edi', callee-saved-restored: false +# CHECK: callee-saved-register: '$edi', callee-saved-restored: false stack: - { id: 0, name: b, offset: -20, size: 4, alignment: 4 } - - { id: 1, offset: -24, size: 4, alignment: 4, callee-saved-register: '%edi', + - { id: 1, offset: -24, size: 4, alignment: 4, callee-saved-register: '$edi', callee-saved-restored: false } body: | bb.0.entry: successors: %bb.1.check - liveins: %edi, %rbx + liveins: $edi, $rbx - frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp - %rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags - %ebx = COPY %edi - MOV32mr %rsp, 1, _, 12, _, %ebx + frame-setup PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp + $rsp = frame-setup SUB64ri8 $rsp, 16, implicit-def dead $eflags + $ebx = COPY $edi + MOV32mr $rsp, 1, _, 12, _, $ebx bb.1.check: successors: %bb.2.loop, %bb.3.exit - liveins: %ebx + liveins: $ebx - CMP32ri8 %ebx, 10, implicit-def %eflags - JG_1 %bb.3.exit, implicit killed %eflags + CMP32ri8 $ebx, 10, implicit-def $eflags + JG_1 %bb.3.exit, implicit killed $eflags JMP_1 %bb.2.loop bb.2.loop: successors: %bb.1.check - liveins: %ebx + liveins: $ebx - %edi = MOV32rm %rsp, 1, _, 12, _ - CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax - %eax = DEC32r killed %eax, implicit-def dead %eflags - MOV32mr %rsp, 1, _, 12, _, killed %eax + $edi = MOV32rm $rsp, 1, _, 12, _ + CALL64pcrel32 @compute, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax + $eax = DEC32r killed $eax, implicit-def dead $eflags + MOV32mr $rsp, 1, _, 12, _, killed $eax JMP_1 %bb.1.check bb.3.exit: - %eax = MOV32r0 implicit-def dead %eflags - %rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags - %rbx = POP64r implicit-def %rsp, implicit %rsp - RETQ %eax + $eax = MOV32r0 implicit-def dead $eflags + $rsp = ADD64ri8 $rsp, 16, implicit-def dead $eflags + $rbx = POP64r implicit-def $rsp, implicit $rsp + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir b/llvm/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir index 2bdec446af0..e6a36bb3dd5 100644 --- a/llvm/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir +++ b/llvm/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir @@ -20,10 +20,10 @@ stack: - { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 } body: | bb.0.entry: - %rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags + $rsp = SUB64ri32 $rsp, 4040, implicit-def dead $eflags ; CHECK: CFI_INSTRUCTION def_cfa_offset 4048 CFI_INSTRUCTION def_cfa_offset 4048 - %rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags + $rsp = ADD64ri32 $rsp, 4040, implicit-def dead $eflags RETQ ... diff --git a/llvm/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir b/llvm/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir index 2afa8e3bf92..a2c5b10cb91 100644 --- a/llvm/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir +++ b/llvm/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir @@ -21,12 +21,12 @@ fixedStack: - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 } body: | bb.0.entry: - liveins: %rbp + liveins: $rbp - PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp + PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp CFI_INSTRUCTION def_cfa_offset 16 - CFI_INSTRUCTION offset %rbp, -16 - %rbp = MOV64rr %rsp - ; CHECK: CFI_INSTRUCTION def_cfa_register %rbp - CFI_INSTRUCTION def_cfa_register %rbp + CFI_INSTRUCTION offset $rbp, -16 + $rbp = MOV64rr $rsp + ; CHECK: CFI_INSTRUCTION def_cfa_register $rbp + CFI_INSTRUCTION def_cfa_register $rbp ... diff --git a/llvm/test/CodeGen/MIR/X86/cfi-offset.mir b/llvm/test/CodeGen/MIR/X86/cfi-offset.mir index 4cb33073f80..b8d9e315081 100644 --- a/llvm/test/CodeGen/MIR/X86/cfi-offset.mir +++ b/llvm/test/CodeGen/MIR/X86/cfi-offset.mir @@ -28,20 +28,20 @@ fixedStack: - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 } body: | bb.0.entry: - liveins: %ecx, %edi, %edx, %esi, %rbx + liveins: $ecx, $edi, $edx, $esi, $rbx - PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp + PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp CFI_INSTRUCTION def_cfa_offset 16 - ; CHECK: CFI_INSTRUCTION offset %rbx, -16 - CFI_INSTRUCTION offset %rbx, -16 - %ebx = COPY %edi, implicit-def %rbx - %ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags - %ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags - %ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags - %edi = COPY %ebx - CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp - %eax = LEA64_32r killed %rbx, 1, %rbx, 0, _ - %rbx = POP64r implicit-def %rsp, implicit %rsp - RETQ %eax + ; CHECK: CFI_INSTRUCTION offset $rbx, -16 + CFI_INSTRUCTION offset $rbx, -16 + $ebx = COPY $edi, implicit-def $rbx + $ebx = ADD32rr $ebx, killed $esi, implicit-def dead $eflags + $ebx = ADD32rr $ebx, killed $edx, implicit-def dead $eflags + $ebx = ADD32rr $ebx, killed $ecx, implicit-def dead $eflags + $edi = COPY $ebx + CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp + $eax = LEA64_32r killed $rbx, 1, $rbx, 0, _ + $rbx = POP64r implicit-def $rsp, implicit $rsp + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/constant-pool.mir b/llvm/test/CodeGen/MIR/X86/constant-pool.mir index 431af44b0c5..69a436b41f3 100644 --- a/llvm/test/CodeGen/MIR/X86/constant-pool.mir +++ b/llvm/test/CodeGen/MIR/X86/constant-pool.mir @@ -61,13 +61,13 @@ constants: alignment: 4 body: | bb.0.entry: - ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.0, %noreg - ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, %noreg, %const.1, %noreg - %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ - %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _ - %xmm1 = CVTSS2SDrr killed %xmm1 - %xmm0 = MULSDrr killed %xmm0, killed %xmm1 - RETQ %xmm0 + ; CHECK: $xmm0 = ADDSDrm killed $xmm0, $rip, 1, $noreg, %const.0, $noreg + ; CHECK-NEXT: $xmm1 = ADDSSrm killed $xmm1, $rip, 1, $noreg, %const.1, $noreg + $xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.0, _ + $xmm1 = ADDSSrm killed $xmm1, $rip, 1, _, %const.1, _ + $xmm1 = CVTSS2SDrr killed $xmm1 + $xmm0 = MULSDrr killed $xmm0, killed $xmm1 + RETQ $xmm0 ... --- # Verify that alignment can be inferred: @@ -89,11 +89,11 @@ constants: value: 'float 6.250000e+00' body: | bb.0.entry: - %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ - %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _ - %xmm1 = CVTSS2SDrr killed %xmm1 - %xmm0 = MULSDrr killed %xmm0, killed %xmm1 - RETQ %xmm0 + $xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.0, _ + $xmm1 = ADDSSrm killed $xmm1, $rip, 1, _, %const.1, _ + $xmm1 = CVTSS2SDrr killed $xmm1 + $xmm0 = MULSDrr killed $xmm0, killed $xmm1 + RETQ $xmm0 ... --- # Verify that the non-standard alignments are respected: @@ -117,13 +117,13 @@ constants: alignment: 1 body: | bb.0.entry: - ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.0, %noreg - ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, %noreg, %const.1, %noreg - %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ - %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _ - %xmm1 = CVTSS2SDrr killed %xmm1 - %xmm0 = MULSDrr killed %xmm0, killed %xmm1 - RETQ %xmm0 + ; CHECK: $xmm0 = ADDSDrm killed $xmm0, $rip, 1, $noreg, %const.0, $noreg + ; CHECK-NEXT: $xmm1 = ADDSSrm killed $xmm1, $rip, 1, $noreg, %const.1, $noreg + $xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.0, _ + $xmm1 = ADDSSrm killed $xmm1, $rip, 1, _, %const.1, _ + $xmm1 = CVTSS2SDrr killed $xmm1 + $xmm0 = MULSDrr killed $xmm0, killed $xmm1 + RETQ $xmm0 ... --- # CHECK: name: test4 @@ -135,11 +135,11 @@ constants: value: 'float 6.250000e+00' body: | bb.0.entry: - ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.1 - 12, %noreg - ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, %noreg, %const.0 + 8, %noreg - %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _ - %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _ - %xmm1 = CVTSS2SDrr killed %xmm1 - %xmm0 = MULSDrr killed %xmm0, killed %xmm1 - RETQ %xmm0 + ; CHECK: $xmm0 = ADDSDrm killed $xmm0, $rip, 1, $noreg, %const.1 - 12, $noreg + ; CHECK-NEXT: $xmm1 = ADDSSrm killed $xmm1, $rip, 1, $noreg, %const.0 + 8, $noreg + $xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.1 - 12, _ + $xmm1 = ADDSSrm killed $xmm1, $rip, 1, _, %const.0 + 8, _ + $xmm1 = CVTSS2SDrr killed $xmm1 + $xmm0 = MULSDrr killed $xmm0, killed $xmm1 + RETQ $xmm0 ... diff --git a/llvm/test/CodeGen/MIR/X86/dead-register-flag.mir b/llvm/test/CodeGen/MIR/X86/dead-register-flag.mir index e6ab458e738..bcfdadf7ac0 100644 --- a/llvm/test/CodeGen/MIR/X86/dead-register-flag.mir +++ b/llvm/test/CodeGen/MIR/X86/dead-register-flag.mir @@ -18,7 +18,7 @@ name: foo body: | ; CHECK: bb.0.body: bb.0.body: - ; CHECK: %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags - %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags - RETQ %eax + ; CHECK: $eax = IMUL32rri8 $edi, 11, implicit-def dead $eflags + $eax = IMUL32rri8 $edi, 11, implicit-def dead $eflags + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/def-register-already-tied-error.mir b/llvm/test/CodeGen/MIR/X86/def-register-already-tied-error.mir index 32d41d264e7..53fb4c6e59b 100644 --- a/llvm/test/CodeGen/MIR/X86/def-register-already-tied-error.mir +++ b/llvm/test/CodeGen/MIR/X86/def-register-already-tied-error.mir @@ -12,13 +12,13 @@ name: test tracksRegLiveness: true liveins: - - { reg: '%rdi' } + - { reg: '$rdi' } body: | bb.0.entry: - liveins: %rdi + liveins: $rdi ; CHECK: [[@LINE+1]]:83: the tied-def operand #3 is already tied with another register operand - INLINEASM &"$foo", 1, 2818058, def %rdi, 2147483657, killed %rdi(tied-def 3), killed %rdi(tied-def 3) - %rax = COPY killed %rdi - RETQ killed %rax + INLINEASM &"$foo", 1, 2818058, def $rdi, 2147483657, killed $rdi(tied-def 3), killed $rdi(tied-def 3) + $rax = COPY killed $rdi + RETQ killed $rax ... diff --git a/llvm/test/CodeGen/MIR/X86/diexpr-win32.mir b/llvm/test/CodeGen/MIR/X86/diexpr-win32.mir index 38c78ee69cd..381b0071f82 100644 --- a/llvm/test/CodeGen/MIR/X86/diexpr-win32.mir +++ b/llvm/test/CodeGen/MIR/X86/diexpr-win32.mir @@ -179,7 +179,7 @@ frameInfo: restorePoint: '' fixedStack: - { id: 0, type: spill-slot, offset: -8, size: 4, alignment: 4, stack-id: 0, - callee-saved-register: '%esi' } + callee-saved-register: '$esi' } - { id: 1, type: default, offset: 4, size: 4, alignment: 4, stack-id: 0, isImmutable: true, isAliased: false, callee-saved-register: '' } - { id: 2, type: default, offset: 0, size: 4, alignment: 4, stack-id: 0, @@ -188,24 +188,24 @@ stack: constants: body: | bb.0.entry: - liveins: %esi + liveins: $esi - frame-setup PUSH32r killed %esi, implicit-def %esp, implicit %esp + frame-setup PUSH32r killed $esi, implicit-def $esp, implicit $esp CFI_INSTRUCTION def_cfa_offset 8 - CFI_INSTRUCTION offset %esi, -8 - %esi = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.2) - DBG_VALUE %esp, 0, !26, !10, debug-location !25 - DBG_VALUE %esp, 0, !23, !DIExpression(DW_OP_plus_uconst, 8, DW_OP_deref), debug-location !25 - CALLpcrel32 @getString, csr_32, implicit %esp, implicit-def %esp, implicit-def %eax, debug-location !29 - %ecx = MOV32rm %eax, 1, _, 0, _, debug-location !29 :: (dereferenceable load 4 from %ir.1) - %edx = MOV32rm %eax, 1, _, 4, _, debug-location !29 :: (dereferenceable load 4 from %ir.1 + 4) - MOV32mr %esi, 1, _, 0, _, killed %ecx, debug-location !29 :: (store 4 into %ir.0) - MOV32mr %esi, 1, _, 4, _, killed %edx, debug-location !29 :: (store 4 into %ir.0 + 4) - %eax = MOV32rm killed %eax, 1, _, 8, _, debug-location !29 :: (dereferenceable load 4 from %ir.1 + 8) - MOV32mr %esi, 1, _, 8, _, killed %eax, debug-location !29 :: (store 4 into %ir.0 + 8) - %eax = COPY killed %esi, debug-location !30 - %esi = POP32r implicit-def %esp, implicit %esp, debug-location !30 - RET 0, %eax, debug-location !30 + CFI_INSTRUCTION offset $esi, -8 + $esi = MOV32rm $esp, 1, _, 8, _ :: (load 4 from %fixed-stack.2) + DBG_VALUE $esp, 0, !26, !10, debug-location !25 + DBG_VALUE $esp, 0, !23, !DIExpression(DW_OP_plus_uconst, 8, DW_OP_deref), debug-location !25 + CALLpcrel32 @getString, csr_32, implicit $esp, implicit-def $esp, implicit-def $eax, debug-location !29 + $ecx = MOV32rm $eax, 1, _, 0, _, debug-location !29 :: (dereferenceable load 4 from %ir.1) + $edx = MOV32rm $eax, 1, _, 4, _, debug-location !29 :: (dereferenceable load 4 from %ir.1 + 4) + MOV32mr $esi, 1, _, 0, _, killed $ecx, debug-location !29 :: (store 4 into %ir.0) + MOV32mr $esi, 1, _, 4, _, killed $edx, debug-location !29 :: (store 4 into %ir.0 + 4) + $eax = MOV32rm killed $eax, 1, _, 8, _, debug-location !29 :: (dereferenceable load 4 from %ir.1 + 8) + MOV32mr $esi, 1, _, 8, _, killed $eax, debug-location !29 :: (store 4 into %ir.0 + 8) + $eax = COPY killed $esi, debug-location !30 + $esi = POP32r implicit-def $esp, implicit $esp, debug-location !30 + RET 0, $eax, debug-location !30 ... --- @@ -244,10 +244,10 @@ stack: constants: body: | bb.0.entry: - %eax = MOV32rm %esp, 1, _, 4, _ :: (load 4 from %fixed-stack.1) - %eax = MOV32rm killed %eax, 1, _, 0, _, debug-location !34 :: (load 4 from %ir.0) - DBG_VALUE debug-use %eax, 0, !35, !DIExpression(DW_OP_constu, 4, DW_OP_minus), debug-location !34 - %eax = ADD32rm killed %eax, %esp, 1, _, 8, _, implicit-def dead %eflags, debug-location !36 :: (load 4 from %fixed-stack.0) - RET 0, %eax, debug-location !36 + $eax = MOV32rm $esp, 1, _, 4, _ :: (load 4 from %fixed-stack.1) + $eax = MOV32rm killed $eax, 1, _, 0, _, debug-location !34 :: (load 4 from %ir.0) + DBG_VALUE debug-use $eax, 0, !35, !DIExpression(DW_OP_constu, 4, DW_OP_minus), debug-location !34 + $eax = ADD32rm killed $eax, $esp, 1, _, 8, _, implicit-def dead $eflags, debug-location !36 :: (load 4 from %fixed-stack.0) + RET 0, $eax, debug-location !36 ... diff --git a/llvm/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir b/llvm/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir index 0c15e84f226..f61f1e015be 100644 --- a/llvm/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir +++ b/llvm/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir @@ -15,13 +15,13 @@ name: volatile_inc tracksRegLiveness: true liveins: - - { reg: '%rdi' } + - { reg: '$rdi' } body: | bb.0.entry: - liveins: %rdi + liveins: $rdi ; CHECK: [[@LINE+1]]:50: duplicate 'volatile' memory operand flag - %eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile volatile load 4 from %ir.x) - %eax = INC32r killed %eax, implicit-def dead %eflags - MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x) - RETQ %eax + $eax = MOV32rm $rdi, 1, _, 0, _ :: (volatile volatile load 4 from %ir.x) + $eax = INC32r killed $eax, implicit-def dead $eflags + MOV32mr killed $rdi, 1, _, 0, _, $eax :: (volatile store 4 into %ir.x) + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir b/llvm/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir index 9d8f4f15930..1347fd04081 100644 --- a/llvm/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir +++ b/llvm/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir @@ -21,15 +21,15 @@ body: | bb.0.entry: successors: %bb.1.less, %bb.2.exit - CMP32ri8 %edi, 10, implicit-def %eflags + CMP32ri8 $edi, 10, implicit-def $eflags ; CHECK: [[@LINE+1]]:31: duplicate 'implicit' register flag - JG_1 %bb.2.exit, implicit implicit %eflags + JG_1 %bb.2.exit, implicit implicit $eflags bb.1.less: - %eax = MOV32r0 implicit-def %eflags - RETQ %eax + $eax = MOV32r0 implicit-def $eflags + RETQ $eax bb.2.exit: - %eax = COPY %edi - RETQ %eax + $eax = COPY $edi + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir b/llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir index 7f345545ffd..3829489e2a9 100644 --- a/llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir +++ b/llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir @@ -21,24 +21,24 @@ name: test tracksRegLiveness: true liveins: - - { reg: '%edi' } - - { reg: '%esi' } + - { reg: '$edi' } + - { reg: '$esi' } frameInfo: stackSize: 8 adjustsStack: true hasCalls: true body: | bb.0.entry: - liveins: %edi, %esi + liveins: $edi, $esi - frame-setup PUSH64r undef %rax, implicit-def %rsp, implicit %rsp + frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp CFI_INSTRUCTION def_cfa_offset 16 - %ecx = COPY %edi - %ecx = ADD32rr killed %ecx, killed %esi, implicit-def dead %eflags - ; CHECK: INLINEASM &nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di - INLINEASM &nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di - %edi = COPY killed %ecx - CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp - %rax = POP64r implicit-def %rsp, implicit %rsp + $ecx = COPY $edi + $ecx = ADD32rr killed $ecx, killed $esi, implicit-def dead $eflags + ; CHECK: INLINEASM &nop, 1, 12, implicit-def dead early-clobber $ax, 12, implicit-def dead early-clobber $di + INLINEASM &nop, 1, 12, implicit-def dead early-clobber $ax, 12, implicit-def dead early-clobber $di + $edi = COPY killed $ecx + CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp + $rax = POP64r implicit-def $rsp, implicit $rsp RETQ ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir index f65a5e6c948..2da222af258 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir @@ -15,16 +15,16 @@ name: memory_alignment tracksRegLiveness: true liveins: - - { reg: '%rdi' } + - { reg: '$rdi' } body: | bb.0.entry: - liveins: %rdi + liveins: $rdi ; CHECK: [[@LINE+1]]:65: expected 'align' - %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, 32) - %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32) - %xmm2 = FsFLD0SS - %xmm1 = MOVSSrr killed %xmm1, killed %xmm2 - MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32) - MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32) + $xmm0 = MOVAPSrm $rdi, 1, _, 0, _ :: (load 16 from %ir.vec, 32) + $xmm1 = MOVAPSrm $rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32) + $xmm2 = FsFLD0SS + $xmm1 = MOVSSrr killed $xmm1, killed $xmm2 + MOVAPSmr $rdi, 1, _, 0, _, killed $xmm0 :: (store 16 into %ir.vec, align 32) + MOVAPSmr killed $rdi, 1, _, 16, _, killed $xmm1 :: (store 16 into %ir.vec + 16, align 32) RETQ ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir index 9bde7bf279a..48239b9a73c 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir @@ -15,16 +15,16 @@ name: memory_alignment tracksRegLiveness: true liveins: - - { reg: '%rdi' } + - { reg: '$rdi' } body: | bb.0.entry: - liveins: %rdi + liveins: $rdi ; CHECK: [[@LINE+1]]:70: expected an integer literal after 'align' - %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align) - %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32) - %xmm2 = FsFLD0SS - %xmm1 = MOVSSrr killed %xmm1, killed %xmm2 - MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32) - MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32) + $xmm0 = MOVAPSrm $rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align) + $xmm1 = MOVAPSrm $rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32) + $xmm2 = FsFLD0SS + $xmm1 = MOVSSrr killed $xmm1, killed $xmm2 + MOVAPSmr $rdi, 1, _, 0, _, killed $xmm0 :: (store 16 into %ir.vec, align 32) + MOVAPSmr killed $rdi, 1, _, 16, _, killed $xmm1 :: (store 16 into %ir.vec + 16, align 32) RETQ ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir b/llvm/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir index 0de5b5bc687..841654fe7cb 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir @@ -19,22 +19,22 @@ name: foo tracksRegLiveness: true liveins: - - { reg: '%edi' } + - { reg: '$edi' } body: | ; CHECK: [[@LINE+1]]:3: expected a basic block definition before instructions successors: %bb.1.less, %bb.2.exit - liveins: %edi 44 + liveins: $edi 44 - CMP32ri8 %edi, 10, implicit-def %eflags - JG_1 %bb.2.exit, implicit killed %eflags + CMP32ri8 $edi, 10, implicit-def $eflags + JG_1 %bb.2.exit, implicit killed $eflags bb.1.less: - %eax = MOV32r0 implicit-def dead %eflags - RETQ killed %eax + $eax = MOV32r0 implicit-def dead $eflags + RETQ killed $eax bb.2.exit: - liveins: %edi + liveins: $edi - %eax = COPY killed %edi - RETQ killed %eax + $eax = COPY killed $edi + RETQ killed $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir b/llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir index c74d42d4dcc..cad3d529df1 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir @@ -21,9 +21,9 @@ body: | bb.0.entry: successors: %bb.1.block ; CHECK: [[@LINE+1]]:51: expected an IR block reference - %rax = LEA64r %rip, 1, _, blockaddress(@test, _), _ - MOV64mr %rip, 1, _, @addr, _, killed %rax - JMP64m %rip, 1, _, @addr, _ + $rax = LEA64r $rip, 1, _, blockaddress(@test, _), _ + MOV64mr $rip, 1, _, @addr, _, killed $rax + JMP64m $rip, 1, _, @addr, _ bb.1.block (address-taken): RETQ diff --git a/llvm/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir b/llvm/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir index eb0d16755c4..f861689b5e9 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir @@ -26,17 +26,17 @@ fixedStack: - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 } body: | bb.0.entry: - PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp + PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp CFI_INSTRUCTION def_cfa_offset 16 ; CHECK: [[@LINE+1]]:33: expected ',' - CFI_INSTRUCTION offset %rbx -16 - %ebx = COPY %edi, implicit-def %rbx - %ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags - %ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags - %ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags - %edi = COPY %ebx - CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp - %eax = LEA64_32r killed %rbx, 1, %rbx, 0, _ - %rbx = POP64r implicit-def %rsp, implicit %rsp - RETQ %eax + CFI_INSTRUCTION offset $rbx -16 + $ebx = COPY $edi, implicit-def $rbx + $ebx = ADD32rr $ebx, killed $esi, implicit-def dead $eflags + $ebx = ADD32rr $ebx, killed $edx, implicit-def dead $eflags + $ebx = ADD32rr $ebx, killed $ecx, implicit-def dead $eflags + $edi = COPY $ebx + CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp + $eax = LEA64_32r killed $rbx, 1, $rbx, 0, _ + $rbx = POP64r implicit-def $rsp, implicit $rsp + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir index f617ddfa0eb..3c49d9dd1c6 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir @@ -15,11 +15,11 @@ name: test tracksRegLiveness: true liveins: - - { reg: '%rdi' } + - { reg: '$rdi' } body: | bb.0.entry2: - liveins: %rdi + liveins: $rdi ; CHECK: [[@LINE+1]]:87: expected ',' before the next machine memory operand - INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir.a) (load 4 from %ir.a) + INC32m killed $rdi, 1, _, 0, _, implicit-def dead $eflags :: (store 4 into %ir.a) (load 4 from %ir.a) RETQ ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir index d96d263a320..748ae76f515 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir @@ -21,14 +21,14 @@ name: foo body: | bb.0.entry: - %eax = MOV32rm %rdi, 1, _, 0, _ - CMP32ri8 %eax, 10, implicit-def %eflags + $eax = MOV32rm $rdi, 1, _, 0, _ + CMP32ri8 $eax, 10, implicit-def $eflags ; CHECK: [[@LINE+1]]:35: missing implicit register operand 'implicit %eflags' - JG_1 %bb.2.exit, implicit %eax + JG_1 %bb.2.exit, implicit $eax bb.1.less: - %eax = MOV32r0 implicit-def %eflags + $eax = MOV32r0 implicit-def $eflags bb.2.exit: - RETQ %eax + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir b/llvm/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir index bd6cf6bd576..90cf680f160 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir @@ -21,14 +21,14 @@ name: foo body: | bb.0.entry: - %eax = MOV32rm %rdi, 1, _, 0, _ - CMP32ri8 %eax, 10, implicit-def %eflags + $eax = MOV32rm $rdi, 1, _, 0, _ + CMP32ri8 $eax, 10, implicit-def $eflags ; CHECK: [[@LINE+1]]:42: missing implicit register operand 'implicit %eflags' - JG_1 %bb.2.exit, implicit-def %eflags + JG_1 %bb.2.exit, implicit-def $eflags bb.1.less: - %eax = MOV32r0 implicit-def %eflags + $eax = MOV32r0 implicit-def $eflags bb.2.exit: - RETQ %eax + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir b/llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir index 2f53023ecdb..067cc5230e4 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir @@ -21,9 +21,9 @@ body: | bb.0.entry: successors: %bb.1.block ; CHECK: [[@LINE+1]]:44: expected an IR function reference - %rax = LEA64r %rip, 1, _, blockaddress(@addr, %ir-block.block), _ - MOV64mr %rip, 1, _, @addr, _, killed %rax - JMP64m %rip, 1, _, @addr, _ + $rax = LEA64r $rip, 1, _, blockaddress(@addr, %ir-block.block), _ + MOV64mr $rip, 1, _, @addr, _, killed $rax + JMP64m $rip, 1, _, @addr, _ bb.1.block (address-taken): RETQ diff --git a/llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir b/llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir index 1cabcfc73c2..a7e87630395 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir @@ -21,9 +21,9 @@ body: | bb.0.entry: successors: %bb.1.block ; CHECK: [[@LINE+1]]:44: expected a global value - %rax = LEA64r %rip, 1, _, blockaddress(0, %ir-block.block), _ - MOV64mr %rip, 1, _, @addr, _, killed %rax - JMP64m %rip, 1, _, @addr, _ + $rax = LEA64r $rip, 1, _, blockaddress(0, %ir-block.block), _ + MOV64mr $rip, 1, _, @addr, _, killed $rax + JMP64m $rip, 1, _, @addr, _ bb.1.block (address-taken): RETQ diff --git a/llvm/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir b/llvm/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir index f2f354b5a7c..3f492a94e2c 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir @@ -17,8 +17,8 @@ name: inc body: | bb.0.entry: ; CHECK: [[@LINE+1]]:37: expected an integer literal after '+' - %rax = MOV64rm %rip, 1, _, @G + , _ - %eax = MOV32rm %rax, 1, _, 0, _ - %eax = INC32r %eax, implicit-def %eflags - RETQ %eax + $rax = MOV64rm $rip, 1, _, @G + , _ + $eax = MOV32rm $rax, 1, _, 0, _ + $eax = INC32r $eax, implicit-def $eflags + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir b/llvm/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir index aa30804aafa..23f64aee32e 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir @@ -12,13 +12,13 @@ name: test tracksRegLiveness: true liveins: - - { reg: '%rdi' } + - { reg: '$rdi' } body: | bb.0.entry: - liveins: %rdi + liveins: $rdi ; CHECK: [[@LINE+1]]:78: expected tied-def or low-level type after '(' - INLINEASM &"$foo", 1, 2818058, def %rdi, 2147483657, killed %rdi(tied-def) - %rax = COPY killed %rdi - RETQ killed %rax + INLINEASM &"$foo", 1, 2818058, def $rdi, 2147483657, killed $rdi(tied-def) + $rax = COPY killed $rdi + RETQ killed $rax ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir b/llvm/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir index e8f06358505..e86eae36f36 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir @@ -21,18 +21,18 @@ body: | bb.0.entry: ; CHECK: [[@LINE+1]]:29: expected an integer literal after '(' successors: %bb.1.less (_), %bb.2.exit(32) - liveins: %edi + liveins: $edi - CMP32ri8 %edi, 10, implicit-def %eflags - JG_1 %bb.2.exit, implicit killed %eflags + CMP32ri8 $edi, 10, implicit-def $eflags + JG_1 %bb.2.exit, implicit killed $eflags bb.1.less: - %eax = MOV32r0 implicit-def dead %eflags - RETQ killed %eax + $eax = MOV32r0 implicit-def dead $eflags + RETQ killed $eax bb.2.exit: - liveins: %edi + liveins: $edi - %eax = COPY killed %edi - RETQ killed %eax + $eax = COPY killed $edi + RETQ killed $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir index 225f767c555..6be0a902ec9 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir @@ -13,11 +13,11 @@ name: test tracksRegLiveness: true liveins: - - { reg: '%rdi' } + - { reg: '$rdi' } body: | bb.0.entry: - liveins: %rdi + liveins: $rdi ; CHECK: [[@LINE+1]]:48: expected 'load' or 'store' memory operation - %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (4 from %ir.a) - RETQ %eax + $eax = MOV32rm killed $rdi, 1, _, 0, _ :: (4 from %ir.a) + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-machine-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-machine-operand.mir index 70fff3daa09..89bec0e5bb3 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-machine-operand.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-machine-operand.mir @@ -13,7 +13,7 @@ name: foo body: | bb.0.entry: ; CHECK: [[@LINE+1]]:20: expected a machine operand - %eax = XOR32rr = - RETQ %eax + $eax = XOR32rr = + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir b/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir index d2729978669..47aff14179a 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir @@ -48,10 +48,10 @@ stack: - { id: 0, name: x.addr, size: 4, alignment: 4 } body: | bb.0.entry: - %0 = COPY %edi + %0 = COPY $edi ; CHECK: [[@LINE+1]]:46: expected a metadata node after 'debug-location' DBG_VALUE _, 0, !12, !13, debug-location 14 - MOV32mr %stack.x.addr, 1, _, 0, _, %0 - %eax = COPY %0 - RETQ %eax + MOV32mr $stack.x.addr, 1, _, 0, _, %0 + $eax = COPY %0 + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir b/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir index 3f668cd815f..394945cdc8f 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir @@ -48,10 +48,10 @@ stack: - { id: 0, name: x.addr, size: 4, alignment: 4 } body: | bb.0.entry: - %0 = COPY %edi + %0 = COPY $edi ; CHECK: [[@LINE+1]]:28: expected metadata id after '!' DBG_VALUE _, 0, !12, ! _ MOV32mr %stack.0.x.addr, 1, _, 0, _, %0 - %eax = COPY %0 - RETQ %eax + $eax = COPY %0 + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir b/llvm/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir index dc8cb02338e..f68dd8641f7 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir @@ -11,15 +11,15 @@ --- name: test liveins: - - { reg: '%edi' } + - { reg: '$edi' } stack: # CHECK: [[@LINE+1]]:74: expected a metadata node - { id: 0, name: xa, offset: -12, size: 4, alignment: 4, di-variable: '0' } body: | bb.0.entry: - liveins: %edi + liveins: $edi - MOV32mr %rsp, 1, _, -4, _, %edi :: (store 4 into %ir.xa) - %eax = COPY killed %edi - RETQ killed %eax + MOV32mr $rsp, 1, _, -4, _, $edi :: (store 4 into %ir.xa) + $eax = COPY killed $edi + RETQ killed $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir b/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir index 9847d027ee0..bca4aa1729f 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir @@ -15,16 +15,16 @@ tracksRegLiveness: true registers: - { id: 0, class: gr32 } # CHECK: - { id: 1, class: gr32, preferred-register: '%0' } - # CHECK: - { id: 2, class: gr32, preferred-register: '%edi' } + # CHECK: - { id: 2, class: gr32, preferred-register: '$edi' } - { id: 1, class: gr32, preferred-register: '%0' } - - { id: 2, class: gr32, preferred-register: '%edi' } + - { id: 2, class: gr32, preferred-register: '$edi' } body: | bb.0.body: - liveins: %edi, %esi + liveins: $edi, $esi - %1 = COPY %esi - %2 = COPY %edi - %2 = IMUL32rr %2, %1, implicit-def dead %eflags - %eax = COPY %2 - RETQ killed %eax + %1 = COPY $esi + %2 = COPY $edi + %2 = IMUL32rr %2, %1, implicit-def dead $eflags + $eax = COPY %2 + RETQ killed $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir b/llvm/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir index 424f7cb21c4..f53beda73d5 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir @@ -34,10 +34,10 @@ name: compute tracksRegLiveness: true body: | bb.0.body: - liveins: %edi + liveins: $edi - %eax = COPY killed %edi - RETQ killed %eax + $eax = COPY killed $edi + RETQ killed $eax ... --- name: func @@ -55,34 +55,34 @@ stack: body: | bb.0.entry: successors: %bb.1.check - liveins: %edi, %rbx + liveins: $edi, $rbx - frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp - %rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags - %ebx = COPY %edi - MOV32mr %rsp, 1, _, 12, _, %ebx + frame-setup PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp + $rsp = frame-setup SUB64ri8 $rsp, 16, implicit-def dead $eflags + $ebx = COPY $edi + MOV32mr $rsp, 1, _, 12, _, $ebx bb.1.check: successors: %bb.2.loop, %bb.3.exit - liveins: %ebx + liveins: $ebx - CMP32ri8 %ebx, 10, implicit-def %eflags - JG_1 %bb.3.exit, implicit killed %eflags + CMP32ri8 $ebx, 10, implicit-def $eflags + JG_1 %bb.3.exit, implicit killed $eflags JMP_1 %bb.2.loop bb.2.loop: successors: %bb.1.check - liveins: %ebx + liveins: $ebx - %edi = MOV32rm %rsp, 1, _, 12, _ - CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax - %eax = DEC32r killed %eax, implicit-def dead %eflags - MOV32mr %rsp, 1, _, 12, _, killed %eax + $edi = MOV32rm $rsp, 1, _, 12, _ + CALL64pcrel32 @compute, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax + $eax = DEC32r killed $eax, implicit-def dead $eflags + MOV32mr $rsp, 1, _, 12, _, killed $eax JMP_1 %bb.1.check bb.3.exit: - %eax = MOV32r0 implicit-def dead %eflags - %rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags - %rbx = POP64r implicit-def %rsp, implicit %rsp - RETQ %eax + $eax = MOV32r0 implicit-def dead $eflags + $rsp = ADD64ri8 $rsp, 16, implicit-def dead $eflags + $rbx = POP64r implicit-def $rsp, implicit $rsp + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-named-register-livein.mir b/llvm/test/CodeGen/MIR/X86/expected-named-register-livein.mir index fcd68d3f614..f2e2eaea651 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-named-register-livein.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-named-register-livein.mir @@ -15,6 +15,6 @@ body: | ; CHECK: [[@LINE+1]]:14: expected a named register liveins: %0 - %eax = COPY %edi - RETQ %eax + $eax = COPY $edi + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir b/llvm/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir index 238d7aa6ffb..d364fc41f8a 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir @@ -19,23 +19,23 @@ name: foo tracksRegLiveness: true liveins: - - { reg: '%edi' } + - { reg: '$edi' } body: | bb.0.entry: successors: %bb.1.less, %bb.2.exit ; CHECK: [[@LINE+1]]:19: expected line break at the end of a list - liveins: %edi 44 + liveins: $edi 44 - CMP32ri8 %edi, 10, implicit-def %eflags - JG_1 %bb.2.exit, implicit killed %eflags + CMP32ri8 $edi, 10, implicit-def $eflags + JG_1 %bb.2.exit, implicit killed $eflags bb.1.less: - %eax = MOV32r0 implicit-def dead %eflags - RETQ killed %eax + $eax = MOV32r0 implicit-def dead $eflags + RETQ killed $eax bb.2.exit: - liveins: %edi + liveins: $edi - %eax = COPY killed %edi - RETQ killed %eax + $eax = COPY killed $edi + RETQ killed $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir b/llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir index 6770031da80..eb570c660ad 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir @@ -20,14 +20,14 @@ name: foo body: | bb.0.entry: - %eax = MOV32rm %rdi, 1, _, 0, _ - CMP32ri8 %eax, 10, implicit-def %eflags + $eax = MOV32rm $rdi, 1, _, 0, _ + CMP32ri8 $eax, 10, implicit-def $eflags ; CHECK: [[@LINE+1]]:14: expected a number after '%bb.' - JG_1 %bb.nah, implicit %eflags + JG_1 %bb.nah, implicit $eflags bb.1.true: - %eax = MOV32r0 implicit-def %eflags + $eax = MOV32r0 implicit-def $eflags bb.2.nah: - RETQ %eax + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir index fd7ad1bb9a4..1cadbecac1f 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir @@ -18,10 +18,10 @@ stack: - { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 } body: | bb.0.entry: - %rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags + $rsp = SUB64ri32 $rsp, 4040, implicit-def dead $eflags ; CHECK: [[@LINE+1]]:36: expected a cfi offset CFI_INSTRUCTION def_cfa_offset _ - %rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags + $rsp = ADD64ri32 $rsp, 4040, implicit-def dead $eflags RETQ ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir index 3d127f855ce..8e19be67499 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir @@ -13,12 +13,12 @@ name: test tracksRegLiveness: true liveins: - - { reg: '%rdi' } + - { reg: '$rdi' } body: | bb.0.entry: - liveins: %rdi + liveins: $rdi ; CHECK: [[@LINE+1]]:60: expected a pointer IR value - %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.b) - RETQ %eax + $eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load 4 from %ir.b) + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir b/llvm/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir index 1119133fc11..112eadf8978 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir @@ -15,16 +15,16 @@ name: memory_alignment tracksRegLiveness: true liveins: - - { reg: '%rdi' } + - { reg: '$rdi' } body: | bb.0.entry: - liveins: %rdi + liveins: $rdi ; CHECK: [[@LINE+1]]:71: expected an integer literal after 'align' - %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align -32) - %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32) - %xmm2 = FsFLD0SS - %xmm1 = MOVSSrr killed %xmm1, killed %xmm2 - MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32) - MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32) + $xmm0 = MOVAPSrm $rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align -32) + $xmm1 = MOVAPSrm $rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32) + $xmm2 = FsFLD0SS + $xmm1 = MOVSSrr killed $xmm1, killed $xmm2 + MOVAPSmr $rdi, 1, _, 0, _, killed $xmm0 :: (store 16 into %ir.vec, align 32) + MOVAPSmr killed $rdi, 1, _, 16, _, killed $xmm1 :: (store 16 into %ir.vec + 16, align 32) RETQ ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir index eb53d629a85..f47fcee4d33 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir @@ -26,17 +26,17 @@ fixedStack: - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 } body: | bb.0.entry: - PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp + PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp CFI_INSTRUCTION def_cfa_offset 16 ; CHECK: [[@LINE+1]]:28: expected a cfi register CFI_INSTRUCTION offset %0, -16 - %ebx = COPY %edi, implicit-def %rbx - %ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags - %ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags - %ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags - %edi = COPY %ebx - CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp - %eax = LEA64_32r killed %rbx, 1, %rbx, 0, _ - %rbx = POP64r implicit-def %rsp, implicit %rsp - RETQ %eax + $ebx = COPY $edi, implicit-def $rbx + $ebx = ADD32rr $ebx, killed $esi, implicit-def dead $eflags + $ebx = ADD32rr $ebx, killed $edx, implicit-def dead $eflags + $ebx = ADD32rr $ebx, killed $ecx, implicit-def dead $eflags + $edi = COPY $ebx + CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp + $eax = LEA64_32r killed $rbx, 1, $rbx, 0, _ + $rbx = POP64r implicit-def $rsp, implicit $rsp + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-register-after-flags.mir b/llvm/test/CodeGen/MIR/X86/expected-register-after-flags.mir index dc679ea7fc2..cc2cd4af19f 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-register-after-flags.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-register-after-flags.mir @@ -15,6 +15,6 @@ name: foo body: | bb.0.entry: ; CHECK: [[@LINE+1]]:33: expected a register after register flags - %eax = MOV32r0 implicit-def 2 - RETQ %eax + $eax = MOV32r0 implicit-def 2 + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir b/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir index 57e11d39723..3666c8499b8 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir @@ -13,12 +13,12 @@ name: test tracksRegLiveness: true liveins: - - { reg: '%rdi' } + - { reg: '$rdi' } body: | bb.0.entry: - liveins: %rdi + liveins: $rdi ; CHECK: [[@LINE+1]]:53: expected an atomic scope, ordering or a size integer literal - %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load from %ir.a) - RETQ %eax + $eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load from %ir.a) + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-stack-object.mir b/llvm/test/CodeGen/MIR/X86/expected-stack-object.mir index c536295c42f..87e99f9404c 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-stack-object.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-stack-object.mir @@ -42,26 +42,26 @@ frameInfo: stackProtector: '0' fixedStack: - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, - callee-saved-register: '%rbx' } + callee-saved-register: '$rbx' } stack: - { id: 0, name: StackGuardSlot, offset: -24, size: 8, alignment: 8 } - { id: 1, name: test, offset: -40, size: 8, alignment: 8 } - { id: 2, name: a, offset: -29, size: 5, alignment: 1 } body: | bb.0.entry: - liveins: %rbx, %rbx + liveins: $rbx, $rbx - frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp - %rsp = frame-setup SUB64ri8 %rsp, 32, implicit-def dead %eflags - %rbx = LOAD_STACK_GUARD :: (invariant load 8 from %ir.__stack_chk_guard) - MOV64mr %rsp, 1, _, 24, _, %rbx - %rsi = LEA64r %rsp, 1, _, 19, _ - MOV64mr %rsp, 1, _, 8, _, %rsi - %rdi = LEA64r %rip, 1, _, @.str, _ - dead %eax = MOV32r0 implicit-def dead %eflags, implicit-def %al - CALL64pcrel32 @printf, csr_64, implicit %rsp, implicit %rdi, implicit %rsi, implicit %al, implicit-def %rsp, implicit-def %eax - CMP64rm killed %rbx, %rsp, 1, _, 24, _, implicit-def %eflags - %rsp = ADD64ri8 %rsp, 32, implicit-def dead %eflags - %rbx = POP64r implicit-def %rsp, implicit %rsp - RETQ %eax + frame-setup PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp + $rsp = frame-setup SUB64ri8 $rsp, 32, implicit-def dead $eflags + $rbx = LOAD_STACK_GUARD :: (invariant load 8 from %ir.__stack_chk_guard) + MOV64mr $rsp, 1, _, 24, _, $rbx + $rsi = LEA64r $rsp, 1, _, 19, _ + MOV64mr $rsp, 1, _, 8, _, $rsi + $rdi = LEA64r $rip, 1, _, @.str, _ + dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $al + CALL64pcrel32 @printf, csr_64, implicit $rsp, implicit $rdi, implicit $rsi, implicit $al, implicit-def $rsp, implicit-def $eax + CMP64rm killed $rbx, $rsp, 1, _, 24, _, implicit-def $eflags + $rsp = ADD64ri8 $rsp, 32, implicit-def dead $eflags + $rbx = POP64r implicit-def $rsp, implicit $rsp + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir b/llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir index e9c49c02348..c06e4601480 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir @@ -17,10 +17,10 @@ registers: - { id: 2, class: gr8 } body: | bb.0.entry: - %0 = COPY %edi + %0 = COPY $edi ; CHECK: [[@LINE+1]]:20: expected a subregister index after '.' %1 = COPY %0 . 42 - %2 = AND8ri %1, 1, implicit-def %eflags - %al = COPY %2 - RETQ %al + %2 = AND8ri %1, 1, implicit-def $eflags + $al = COPY %2 + RETQ $al ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-target-flag-name.mir b/llvm/test/CodeGen/MIR/X86/expected-target-flag-name.mir index c3ee45d9660..02e18434d19 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-target-flag-name.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-target-flag-name.mir @@ -17,8 +17,8 @@ name: inc body: | bb.0.entry: ; CHECK: [[@LINE+1]]:46: expected the name of the target flag - %rax = MOV64rm %rip, 1, _, target-flags( ) @G, _ - %eax = MOV32rm killed %rax, 1, _, 0, _ - %eax = INC32r killed %eax, implicit-def dead %eflags - RETQ %eax + $rax = MOV64rm $rip, 1, _, target-flags( ) @G, _ + $eax = MOV32rm killed $rax, 1, _, 0, _ + $eax = INC32r killed $eax, implicit-def dead $eflags + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir b/llvm/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir index ce2dfed4028..ff97bd9f0a1 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir @@ -12,13 +12,13 @@ name: test tracksRegLiveness: true liveins: - - { reg: '%rdi' } + - { reg: '$rdi' } body: | bb.0.entry: - liveins: %rdi + liveins: $rdi ; CHECK: [[@LINE+1]]:70: expected tied-def or low-level type after '(' - INLINEASM &"$foo", 1, 2818058, def %rdi, 2147483657, killed %rdi(3) - %rax = COPY killed %rdi - RETQ killed %rax + INLINEASM &"$foo", 1, 2818058, def $rdi, 2147483657, killed $rdi(3) + $rax = COPY killed $rdi + RETQ killed $rax ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir index a76202eb55b..4beaa2477b1 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir @@ -13,12 +13,12 @@ name: test tracksRegLiveness: true liveins: - - { reg: '%rdi' } + - { reg: '$rdi' } body: | bb.0.entry: - liveins: %rdi + liveins: $rdi ; CHECK: [[@LINE+1]]:60: expected an IR value reference - %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from a) - RETQ %eax + $eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load 4 from a) + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir b/llvm/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir index e5b0183c44d..1f4f8360178 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir @@ -15,12 +15,12 @@ registers: - { id: 0, class: gr32 } liveins: # CHECK: [[@LINE+1]]:34: expected a virtual register - - { reg: '%edi', virtual-reg: '%edi' } + - { reg: '$edi', virtual-reg: '$edi' } body: | bb.0.body: - liveins: %edi + liveins: $edi - %0 = COPY %edi - %eax = COPY %0 - RETQ %eax + %0 = COPY $edi + $eax = COPY %0 + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/external-symbol-operands.mir b/llvm/test/CodeGen/MIR/X86/external-symbol-operands.mir index edc432d8b47..5a13765febb 100644 --- a/llvm/test/CodeGen/MIR/X86/external-symbol-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/external-symbol-operands.mir @@ -32,21 +32,21 @@ tracksRegLiveness: true body: | bb.0.entry: successors: %bb.1.entry, %bb.2.entry - liveins: %edi + liveins: $edi - %rsp = SUB64ri32 %rsp, 520, implicit-def %eflags - %rcx = LOAD_STACK_GUARD - MOV64mr %rsp, 1, _, 512, _, %rcx - %rax = MOVSX64rr32 %edi - %eax = MOV32rm %rsp, 4, %rax, 0, _ - CMP64rm %rcx, %rsp, 1, _, 512, _, implicit-def %eflags - JNE_1 %bb.2.entry, implicit %eflags + $rsp = SUB64ri32 $rsp, 520, implicit-def $eflags + $rcx = LOAD_STACK_GUARD + MOV64mr $rsp, 1, _, 512, _, $rcx + $rax = MOVSX64rr32 $edi + $eax = MOV32rm $rsp, 4, $rax, 0, _ + CMP64rm $rcx, $rsp, 1, _, 512, _, implicit-def $eflags + JNE_1 %bb.2.entry, implicit $eflags bb.1.entry: - liveins: %eax + liveins: $eax - %rsp = ADD64ri32 %rsp, 520, implicit-def %eflags - RETQ %eax + $rsp = ADD64ri32 $rsp, 520, implicit-def $eflags + RETQ $eax bb.2.entry: ; CHECK: CALL64pcrel32 &__stack_chk_fail, @@ -55,10 +55,10 @@ body: | ; CHECK-NEXT: CALL64pcrel32 &"$Quoted \09 External symbol \11 ", ; CHECK-NEXT: CALL64pcrel32 &__stack_chk_fail + 2, ; CHECK-NEXT: CALL64pcrel32 &" check stack - 20" - 20, - CALL64pcrel32 &__stack_chk_fail, csr_64, implicit %rsp, implicit-def %rsp - CALL64pcrel32 &__stack_chk_fail.09-_, csr_64, implicit %rsp, implicit-def %rsp - CALL64pcrel32 &__stack_chk_fail$, csr_64, implicit %rsp, implicit-def %rsp - CALL64pcrel32 &"$Quoted \09 External symbol \11 ", csr_64, implicit %rsp, implicit-def %rsp - CALL64pcrel32 &__stack_chk_fail + 2, csr_64, implicit %rsp, implicit-def %rsp - CALL64pcrel32 &" check stack - 20" - 20, csr_64, implicit %rsp, implicit-def %rsp + CALL64pcrel32 &__stack_chk_fail, csr_64, implicit $rsp, implicit-def $rsp + CALL64pcrel32 &__stack_chk_fail.09-_, csr_64, implicit $rsp, implicit-def $rsp + CALL64pcrel32 &__stack_chk_fail$, csr_64, implicit $rsp, implicit-def $rsp + CALL64pcrel32 &"$Quoted \09 External symbol \11 ", csr_64, implicit $rsp, implicit-def $rsp + CALL64pcrel32 &__stack_chk_fail + 2, csr_64, implicit $rsp, implicit-def $rsp + CALL64pcrel32 &" check stack - 20" - 20, csr_64, implicit $rsp, implicit-def $rsp ... diff --git a/llvm/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir b/llvm/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir index 92ceb1e78e0..aac6dbfe5da 100644 --- a/llvm/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir @@ -28,12 +28,12 @@ stack: - { id: 0, name: b, offset: -8, size: 4, alignment: 4 } body: | bb.0.entry: - frame-setup PUSH32r undef %eax, implicit-def %esp, implicit %esp + frame-setup PUSH32r undef $eax, implicit-def $esp, implicit $esp CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: name: test - ; CHECK: %eax = MOV32rm %esp, 1, %noreg, 8, %noreg :: (load 4 from %fixed-stack.0, align 16) - %eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16) - MOV32mr %esp, 1, _, 0, _, %eax :: (store 4 into %ir.b) - %edx = POP32r implicit-def %esp, implicit %esp - RETL %eax + ; CHECK: $eax = MOV32rm $esp, 1, $noreg, 8, $noreg :: (load 4 from %fixed-stack.0, align 16) + $eax = MOV32rm $esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16) + MOV32mr $esp, 1, _, 0, _, $eax :: (store 4 into %ir.b) + $edx = POP32r implicit-def $esp, implicit $esp + RETL $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir b/llvm/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir index d1b7c1633c2..160e0eaccc3 100644 --- a/llvm/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir +++ b/llvm/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir @@ -22,7 +22,7 @@ fixedStack: - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false } body: | bb.0.entry: - %eax = MOV32rm %esp, 1, _, 4, _ - %eax = ADD32rm killed %eax, %esp, 1, _, 8, _, implicit-def dead %eflags - RETL %eax + $eax = MOV32rm $esp, 1, _, 4, _ + $eax = ADD32rm killed $eax, $esp, 1, _, 8, _, implicit-def dead $eflags + RETL $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/fixed-stack-objects.mir b/llvm/test/CodeGen/MIR/X86/fixed-stack-objects.mir index 93544c426c3..12917fde1d7 100644 --- a/llvm/test/CodeGen/MIR/X86/fixed-stack-objects.mir +++ b/llvm/test/CodeGen/MIR/X86/fixed-stack-objects.mir @@ -28,7 +28,7 @@ stack: - { id: 0, offset: -8, size: 4, alignment: 4 } body: | bb.0.entry: - %eax = MOV32rm %esp, 1, _, 8, _ - MOV32mr %esp, 1, _, 0, _, %eax - RETL %eax + $eax = MOV32rm $esp, 1, _, 8, _ + MOV32mr $esp, 1, _, 0, _, $eax + RETL $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir b/llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir index f5d63287aff..bf3bd06f723 100644 --- a/llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir +++ b/llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir @@ -27,8 +27,8 @@ name: foo tracksRegLiveness: true liveins: - - { reg: '%edi' } - - { reg: '%esi' } + - { reg: '$edi' } + - { reg: '$esi' } # CHECK: frameInfo: # CHECK: savePoint: '%bb.2' # CHECK-NEXT: restorePoint: '%bb.2' @@ -43,31 +43,31 @@ stack: body: | bb.0: successors: %bb.2, %bb.1 - liveins: %edi, %esi + liveins: $edi, $esi - %eax = COPY %edi - CMP32rr %eax, killed %esi, implicit-def %eflags - JL_1 %bb.2, implicit killed %eflags + $eax = COPY $edi + CMP32rr $eax, killed $esi, implicit-def $eflags + JL_1 %bb.2, implicit killed $eflags bb.1: successors: %bb.3 - liveins: %eax + liveins: $eax JMP_1 %bb.3 bb.2.true: successors: %bb.3 - liveins: %eax + liveins: $eax - MOV32mr %stack.0.tmp, 1, _, 0, _, killed %eax - ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %ssp, implicit-def dead %eflags, implicit %rsp, implicit %ssp - %rsi = LEA64r %stack.0.tmp, 1, _, 0, _ - %edi = MOV32r0 implicit-def dead %eflags - CALL64pcrel32 @doSomething, csr_64, implicit %rsp, implicit %ssp, implicit %edi, implicit %rsi, implicit-def %rsp, implicit-def %ssp, implicit-def %eax - ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %ssp, implicit-def dead %eflags, implicit %rsp, implicit %ssp + MOV32mr %stack.0.tmp, 1, _, 0, _, killed $eax + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $ssp, implicit-def dead $eflags, implicit $rsp, implicit $ssp + $rsi = LEA64r %stack.0.tmp, 1, _, 0, _ + $edi = MOV32r0 implicit-def dead $eflags + CALL64pcrel32 @doSomething, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit $rsi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $ssp, implicit-def dead $eflags, implicit $rsp, implicit $ssp bb.3.false: - liveins: %eax + liveins: $eax - RETQ %eax + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir b/llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir index 5aa10afa3c1..2fc27159611 100644 --- a/llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir +++ b/llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir @@ -45,7 +45,7 @@ frameInfo: stackProtector: '%stack.0.StackGuardSlot' fixedStack: - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, - callee-saved-register: '%rbx' } + callee-saved-register: '$rbx' } stack: - { id: 0, name: StackGuardSlot, offset: -24, size: 8, alignment: 8 } - { id: 1, name: test, offset: -40, size: 8, alignment: 8 } @@ -53,27 +53,27 @@ stack: body: | bb.0.entry: successors: %bb.1.entry, %bb.2.entry - liveins: %rbx, %rbx + liveins: $rbx, $rbx - frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp - %rsp = frame-setup SUB64ri8 %rsp, 32, implicit-def dead %eflags - %rbx = LOAD_STACK_GUARD :: (invariant load 8 from @__stack_chk_guard) - MOV64mr %rsp, 1, _, 24, _, %rbx - %rsi = LEA64r %rsp, 1, _, 19, _ - MOV64mr %rsp, 1, _, 8, _, %rsi - %rdi = LEA64r %rip, 1, _, @.str, _ - dead %eax = MOV32r0 implicit-def dead %eflags, implicit-def %al - CALL64pcrel32 @printf, csr_64, implicit %rsp, implicit %rdi, implicit %rsi, implicit %al, implicit-def %rsp, implicit-def %eax - CMP64rm killed %rbx, %rsp, 1, _, 24, _, implicit-def %eflags - JNE_1 %bb.2.entry, implicit %eflags + frame-setup PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp + $rsp = frame-setup SUB64ri8 $rsp, 32, implicit-def dead $eflags + $rbx = LOAD_STACK_GUARD :: (invariant load 8 from @__stack_chk_guard) + MOV64mr $rsp, 1, _, 24, _, $rbx + $rsi = LEA64r $rsp, 1, _, 19, _ + MOV64mr $rsp, 1, _, 8, _, $rsi + $rdi = LEA64r $rip, 1, _, @.str, _ + dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $al + CALL64pcrel32 @printf, csr_64, implicit $rsp, implicit $rdi, implicit $rsi, implicit $al, implicit-def $rsp, implicit-def $eax + CMP64rm killed $rbx, $rsp, 1, _, 24, _, implicit-def $eflags + JNE_1 %bb.2.entry, implicit $eflags bb.1.entry: - liveins: %eax + liveins: $eax - %rsp = ADD64ri8 %rsp, 32, implicit-def dead %eflags - %rbx = POP64r implicit-def %rsp, implicit %rsp - RETQ %eax + $rsp = ADD64ri8 $rsp, 32, implicit-def dead $eflags + $rbx = POP64r implicit-def $rsp, implicit $rsp + RETQ $eax bb.2.entry: - CALL64pcrel32 &__stack_chk_fail, csr_64, implicit %rsp, implicit-def %rsp + CALL64pcrel32 &__stack_chk_fail, csr_64, implicit $rsp, implicit-def $rsp ... diff --git a/llvm/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir b/llvm/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir index 65a852fd860..98fc57da38d 100644 --- a/llvm/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir +++ b/llvm/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir @@ -20,17 +20,17 @@ name: compute body: | bb.0.body: - %eax = IMUL32rri8 %edi, 11, implicit-def %eflags - RETQ %eax + $eax = IMUL32rri8 $edi, 11, implicit-def $eflags + RETQ $eax ... --- name: foo body: | bb.0.entry: - ; CHECK: frame-setup PUSH64r %rax - frame-setup PUSH64r %rax, implicit-def %rsp, implicit %rsp - CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax - ; CHECK: %rdx = frame-destroy POP64r - %rdx = frame-destroy POP64r implicit-def %rsp, implicit %rsp - RETQ %eax + ; CHECK: frame-setup PUSH64r $rax + frame-setup PUSH64r $rax, implicit-def $rsp, implicit $rsp + CALL64pcrel32 @compute, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax + ; CHECK: $rdx = frame-destroy POP64r + $rdx = frame-destroy POP64r implicit-def $rsp, implicit $rsp + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/function-liveins.mir b/llvm/test/CodeGen/MIR/X86/function-liveins.mir index a388bfac3b0..2f3cb6d11ee 100644 --- a/llvm/test/CodeGen/MIR/X86/function-liveins.mir +++ b/llvm/test/CodeGen/MIR/X86/function-liveins.mir @@ -19,18 +19,18 @@ registers: - { id: 1, class: gr32 } - { id: 2, class: gr32 } # CHECK: liveins: -# CHECK-NEXT: - { reg: '%edi', virtual-reg: '%0' } -# CHECK-NEXT: - { reg: '%esi', virtual-reg: '%1' } +# CHECK-NEXT: - { reg: '$edi', virtual-reg: '%0' } +# CHECK-NEXT: - { reg: '$esi', virtual-reg: '%1' } liveins: - - { reg: '%edi', virtual-reg: '%0' } - - { reg: '%esi', virtual-reg: '%1' } + - { reg: '$edi', virtual-reg: '%0' } + - { reg: '$esi', virtual-reg: '%1' } body: | bb.0.body: - liveins: %edi, %esi + liveins: $edi, $esi - %1 = COPY %esi - %0 = COPY %edi - %2 = ADD32rr %0, %1, implicit-def dead %eflags - %eax = COPY %2 - RETQ %eax + %1 = COPY $esi + %0 = COPY $edi + %2 = ADD32rr %0, %1, implicit-def dead $eflags + $eax = COPY %2 + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir b/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir index 6711eb176b2..a0948319878 100644 --- a/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir +++ b/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir @@ -36,11 +36,11 @@ registers: - { id: 8, class: _ } body: | bb.0: - liveins: %edi, %xmm0 + liveins: $edi, $xmm0 ; CHECK: %1:_(s32) = G_ADD %0 - %0(s32) = COPY %edi - %6(<4 x s32>) = COPY %xmm0 - %7(s64) = COPY %rdi + %0(s32) = COPY $edi + %6(<4 x s32>) = COPY $xmm0 + %7(s64) = COPY $rdi %1(s32) = G_ADD %0, %0 ; CHECK: %2:_(<4 x s32>) = G_ADD %6, %6 diff --git a/llvm/test/CodeGen/MIR/X86/global-value-operands.mir b/llvm/test/CodeGen/MIR/X86/global-value-operands.mir index 8c8dee9214f..6287f99e398 100644 --- a/llvm/test/CodeGen/MIR/X86/global-value-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/global-value-operands.mir @@ -64,22 +64,22 @@ name: inc body: | bb.0.entry: - ; CHECK: %rax = MOV64rm %rip, 1, %noreg, @G, %noreg - %rax = MOV64rm %rip, 1, _, @G, _ - %eax = MOV32rm %rax, 1, _, 0, _ - %eax = INC32r %eax, implicit-def %eflags - RETQ %eax + ; CHECK: $rax = MOV64rm $rip, 1, $noreg, @G, $noreg + $rax = MOV64rm $rip, 1, _, @G, _ + $eax = MOV32rm $rax, 1, _, 0, _ + $eax = INC32r $eax, implicit-def $eflags + RETQ $eax ... --- # CHECK: name: inc2 name: inc2 body: | bb.0.entry: - ; CHECK: %rax = MOV64rm %rip, 1, %noreg, @0, %noreg - %rax = MOV64rm %rip, 1, _, @0, _ - %eax = MOV32rm %rax, 1, _, 0, _ - %eax = INC32r %eax, implicit-def %eflags - RETQ %eax + ; CHECK: $rax = MOV64rm $rip, 1, $noreg, @0, $noreg + $rax = MOV64rm $rip, 1, _, @0, _ + $eax = MOV32rm $rax, 1, _, 0, _ + $eax = INC32r $eax, implicit-def $eflags + RETQ $eax ... --- name: test @@ -89,24 +89,24 @@ body: | ; CHECK: , @-_-, ; CHECK: , @_-_a, ; CHECK: , @"$.-B", - %rax = MOV64rm %rip, 1, _, @.$0, _ - %eax = MOV32rm killed %rax, 1, _, 0, _ - %rcx = MOV64rm %rip, 1, _, @-_-, _ - MOV32mr killed %rcx, 1, _, 0, _, killed %eax - %rax = MOV64rm %rip, 1, _, @_-_a, _ - %eax = MOV32rm killed %rax, 1, _, 0, _ - %rcx = MOV64rm %rip, 1, _, @$.-B, _ - MOV32mr killed %rcx, 1, _, 0, _, %eax - RETQ %eax + $rax = MOV64rm $rip, 1, _, @.$0, _ + $eax = MOV32rm killed $rax, 1, _, 0, _ + $rcx = MOV64rm $rip, 1, _, @-_-, _ + MOV32mr killed $rcx, 1, _, 0, _, killed $eax + $rax = MOV64rm $rip, 1, _, @_-_a, _ + $eax = MOV32rm killed $rax, 1, _, 0, _ + $rcx = MOV64rm $rip, 1, _, @$.-B, _ + MOV32mr killed $rcx, 1, _, 0, _, $eax + RETQ $eax ... --- name: test2 body: | bb.0.entry: ; CHECK: , @"\01Hello@$%09 \5C World,", - %rax = MOV64rm %rip, 1, _, @"\01Hello@$%09 \\ World,", _ - %eax = MOV32rm killed %rax, 1, _, 0, _ - RETQ %eax + $rax = MOV64rm $rip, 1, _, @"\01Hello@$%09 \\ World,", _ + $eax = MOV32rm killed $rax, 1, _, 0, _ + RETQ $eax ... --- # CHECK: name: test3 @@ -117,24 +117,24 @@ body: | ; CHECK: , @-_-, ; CHECK: , @_-_a + 4, ; CHECK: , @"$.-B" - 8, - %rax = MOV64rm %rip, 1, _, @.$0 + 0, _ - %eax = MOV32rm killed %rax, 1, _, 0, _ - %rcx = MOV64rm %rip, 1, _, @-_- - 0, _ - MOV32mr killed %rcx, 1, _, 0, _, killed %eax - %rax = MOV64rm %rip, 1, _, @_-_a + 4, _ - %eax = MOV32rm killed %rax, 1, _, 0, _ - %rcx = MOV64rm %rip, 1, _, @$.-B - 8, _ - MOV32mr killed %rcx, 1, _, 0, _, %eax - RETQ %eax + $rax = MOV64rm $rip, 1, _, @.$0 + 0, _ + $eax = MOV32rm killed $rax, 1, _, 0, _ + $rcx = MOV64rm $rip, 1, _, @-_- - 0, _ + MOV32mr killed $rcx, 1, _, 0, _, killed $eax + $rax = MOV64rm $rip, 1, _, @_-_a + 4, _ + $eax = MOV32rm killed $rax, 1, _, 0, _ + $rcx = MOV64rm $rip, 1, _, @$.-B - 8, _ + MOV32mr killed $rcx, 1, _, 0, _, $eax + RETQ $eax ... --- # CHECK: name: tf name: tf body: | bb.0.entry: - ; CHECK: %rax = MOV64rm %rip, 1, %noreg, target-flags(x86-gotpcrel) @G, %noreg - %rax = MOV64rm %rip, 1, _, target-flags(x86-gotpcrel) @G, _ - %eax = MOV32rm %rax, 1, _, 0, _ - %eax = INC32r %eax, implicit-def %eflags - RETQ %eax + ; CHECK: $rax = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @G, $noreg + $rax = MOV64rm $rip, 1, _, target-flags(x86-gotpcrel) @G, _ + $eax = MOV32rm $rax, 1, _, 0, _ + $eax = INC32r $eax, implicit-def $eflags + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/immediate-operands.mir b/llvm/test/CodeGen/MIR/X86/immediate-operands.mir index 4d47219bf3b..05aa89cb8e3 100644 --- a/llvm/test/CodeGen/MIR/X86/immediate-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/immediate-operands.mir @@ -19,18 +19,18 @@ name: foo body: | bb.0.entry: - ; CHECK: %eax = MOV32ri 42 - ; CHECK-NEXT: RETQ %eax - %eax = MOV32ri 42 - RETQ %eax + ; CHECK: $eax = MOV32ri 42 + ; CHECK-NEXT: RETQ $eax + $eax = MOV32ri 42 + RETQ $eax ... --- # CHECK: name: bar name: bar body: | bb.0.entry: - ; CHECK: %eax = MOV32ri -11 - ; CHECK-NEXT: RETQ %eax - %eax = MOV32ri -11 - RETQ %eax + ; CHECK: $eax = MOV32ri -11 + ; CHECK-NEXT: RETQ $eax + $eax = MOV32ri -11 + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/implicit-register-flag.mir b/llvm/test/CodeGen/MIR/X86/implicit-register-flag.mir index dddbfc90cf6..e3f58f6fdae 100644 --- a/llvm/test/CodeGen/MIR/X86/implicit-register-flag.mir +++ b/llvm/test/CodeGen/MIR/X86/implicit-register-flag.mir @@ -32,19 +32,19 @@ name: foo body: | bb.0.entry: successors: %bb.1, %bb.2 - ; CHECK: CMP32ri8 %edi, 10, implicit-def %eflags - ; CHECK-NEXT: JG_1 %bb.2, implicit %eflags - CMP32ri8 %edi, 10, implicit-def %eflags - JG_1 %bb.2, implicit %eflags + ; CHECK: CMP32ri8 $edi, 10, implicit-def $eflags + ; CHECK-NEXT: JG_1 %bb.2, implicit $eflags + CMP32ri8 $edi, 10, implicit-def $eflags + JG_1 %bb.2, implicit $eflags bb.1.less: - ; CHECK: %eax = MOV32r0 implicit-def %eflags - %eax = MOV32r0 implicit-def %eflags - RETQ %eax + ; CHECK: $eax = MOV32r0 implicit-def $eflags + $eax = MOV32r0 implicit-def $eflags + RETQ $eax bb.2.exit: - %eax = COPY %edi - RETQ %eax + $eax = COPY $edi + RETQ $eax ... --- name: implicit_subregister1 @@ -53,16 +53,16 @@ body: | ; Verify that the implicit register verifier won't report an error on implicit ; subregisters. ; CHECK-LABEL: name: implicit_subregister1 - ; CHECK: dead %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags, implicit-def %al - dead %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags, implicit-def %al - RETQ killed %al + ; CHECK: dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al + dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al + RETQ killed $al ... --- name: implicit_subregister2 body: | bb.0.entry: ; CHECK-LABEL: name: implicit_subregister2 - ; CHECK: dead %r15 = XOR64rr undef %r15, undef %r15, implicit-def dead %eflags, implicit-def %r15w - dead %r15 = XOR64rr undef %r15, undef %r15, implicit-def dead %eflags, implicit-def %r15w - RETQ killed %r15w + ; CHECK: dead $r15 = XOR64rr undef $r15, undef $r15, implicit-def dead $eflags, implicit-def $r15w + dead $r15 = XOR64rr undef $r15, undef $r15, implicit-def dead $eflags, implicit-def $r15w + RETQ killed $r15w ... diff --git a/llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir b/llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir index 2a6e91c484a..3403ac86737 100644 --- a/llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir +++ b/llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir @@ -21,32 +21,32 @@ name: test tracksRegLiveness: true liveins: - - { reg: '%rdi' } - - { reg: '%rsi' } + - { reg: '$rdi' } + - { reg: '$rsi' } body: | bb.0.entry: - liveins: %rdi, %rsi + liveins: $rdi, $rsi ; CHECK-LABEL: name: test - ; CHECK: INLINEASM &foo, 0, 2818058, def %rsi, 2818058, def dead %rdi, - INLINEASM &foo, 0, 2818058, def %rsi, 2818058, def dead %rdi, 2147549193, killed %rdi, 2147483657, killed %rsi, 12, implicit-def dead early-clobber %eflags - %rax = MOV64rr killed %rsi - RETQ killed %rax + ; CHECK: INLINEASM &foo, 0, 2818058, def $rsi, 2818058, def dead $rdi, + INLINEASM &foo, 0, 2818058, def $rsi, 2818058, def dead $rdi, 2147549193, killed $rdi, 2147483657, killed $rsi, 12, implicit-def dead early-clobber $eflags + $rax = MOV64rr killed $rsi + RETQ killed $rax ... --- name: test2 tracksRegLiveness: true liveins: - - { reg: '%rdi' } - - { reg: '%rsi' } + - { reg: '$rdi' } + - { reg: '$rsi' } body: | bb.0.entry: - liveins: %rdi, %rsi + liveins: $rdi, $rsi ; Verify that the register ties are preserved. ; CHECK-LABEL: name: test2 - ; CHECK: INLINEASM &foo, 0, 2818058, def %rsi, 2818058, def dead %rdi, 2147549193, killed %rdi(tied-def 5), 2147483657, killed %rsi(tied-def 3), 12, implicit-def dead early-clobber %eflags - INLINEASM &foo, 0, 2818058, def %rsi, 2818058, def dead %rdi, 2147549193, killed %rdi(tied-def 5), 2147483657, killed %rsi(tied-def 3), 12, implicit-def dead early-clobber %eflags - %rax = MOV64rr killed %rsi - RETQ killed %rax + ; CHECK: INLINEASM &foo, 0, 2818058, def $rsi, 2818058, def dead $rdi, 2147549193, killed $rdi(tied-def 5), 2147483657, killed $rsi(tied-def 3), 12, implicit-def dead early-clobber $eflags + INLINEASM &foo, 0, 2818058, def $rsi, 2818058, def dead $rdi, 2147549193, killed $rdi(tied-def 5), 2147483657, killed $rsi(tied-def 3), 12, implicit-def dead early-clobber $eflags + $rax = MOV64rr killed $rsi + RETQ killed $rax ... diff --git a/llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir b/llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir index c49dfec53bb..e1dfb79a111 100644 --- a/llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir +++ b/llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir @@ -58,15 +58,15 @@ stack: - { id: 0, name: x.addr, size: 4, alignment: 4 } body: | bb.0.entry: - liveins: %edi - ; CHECK: DBG_VALUE debug-use %noreg, 0, !11, !DIExpression(), debug-location !12 - ; CHECK: %eax = COPY %0, debug-location !13 - ; CHECK: RETQ %eax, debug-location !13 - %0 = COPY %edi + liveins: $edi + ; CHECK: DBG_VALUE debug-use $noreg, 0, !11, !DIExpression(), debug-location !12 + ; CHECK: $eax = COPY %0, debug-location !13 + ; CHECK: RETQ $eax, debug-location !13 + %0 = COPY $edi DBG_VALUE debug-use _, 0, !12, !DIExpression(), debug-location !13 MOV32mr %stack.0.x.addr, 1, _, 0, _, %0 - %eax = COPY %0, debug-location !14 - RETQ %eax, debug-location !14 + $eax = COPY %0, debug-location !14 + RETQ $eax, debug-location !14 ... --- name: test_typed_immediates @@ -79,16 +79,16 @@ stack: - { id: 0, name: x.addr, size: 4, alignment: 4 } body: | bb.0.entry: - liveins: %edi + liveins: $edi - %0 = COPY %edi - ; CHECK: DBG_VALUE %noreg, i32 0, !DIExpression(), !12 - ; CHECK-NEXT: DBG_VALUE %noreg, i64 -22, !DIExpression(), !12 - ; CHECK-NEXT: DBG_VALUE %noreg, i128 123492148938512984928424384934328985928, !DIExpression(), !12 + %0 = COPY $edi + ; CHECK: DBG_VALUE $noreg, i32 0, !DIExpression(), !12 + ; CHECK-NEXT: DBG_VALUE $noreg, i64 -22, !DIExpression(), !12 + ; CHECK-NEXT: DBG_VALUE $noreg, i128 123492148938512984928424384934328985928, !DIExpression(), !12 DBG_VALUE _, i32 0, !DIExpression(), !13 DBG_VALUE _, i64 -22, !DIExpression(), !13 DBG_VALUE _, i128 123492148938512984928424384934328985928, !DIExpression(), !13 MOV32mr %stack.0.x.addr, 1, _, 0, _, %0 - %eax = COPY %0 - RETQ %eax + $eax = COPY %0 + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir b/llvm/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir index 0b1eb2f5275..45c0b813acb 100644 --- a/llvm/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir +++ b/llvm/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir @@ -19,7 +19,7 @@ constants: body: | bb.0.entry: ; CHECK: [[@LINE+1]]:47: use of undefined constant '%const.10' - %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.10, _ - RETQ %xmm0 + $xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.10, _ + RETQ $xmm0 ... diff --git a/llvm/test/CodeGen/MIR/X86/invalid-target-flag-name.mir b/llvm/test/CodeGen/MIR/X86/invalid-target-flag-name.mir index 1cc9bed2349..9e65f2ae2bd 100644 --- a/llvm/test/CodeGen/MIR/X86/invalid-target-flag-name.mir +++ b/llvm/test/CodeGen/MIR/X86/invalid-target-flag-name.mir @@ -17,8 +17,8 @@ name: inc body: | bb.0.entry: ; CHECK: [[@LINE+1]]:45: use of undefined target flag 'x86-test' - %rax = MOV64rm %rip, 1, _, target-flags(x86-test) @G, _ - %eax = MOV32rm killed %rax, 1, _, 0, _ - %eax = INC32r killed %eax, implicit-def dead %eflags - RETQ %eax + $rax = MOV64rm $rip, 1, _, target-flags(x86-test) @G, _ + $eax = MOV32rm killed $rax, 1, _, 0, _ + $eax = INC32r killed $eax, implicit-def dead $eflags + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir b/llvm/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir index aac3cecc96f..abfa5682ec8 100644 --- a/llvm/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir +++ b/llvm/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir @@ -12,13 +12,13 @@ name: test tracksRegLiveness: true liveins: - - { reg: '%rdi' } + - { reg: '$rdi' } body: | bb.0.entry: - liveins: %rdi + liveins: $rdi ; CHECK: [[@LINE+1]]:58: use of invalid tied-def operand index '300'; instruction has only 6 operands - INLINEASM &"$foo", 1, 2818058, def %rdi, 2147483657, killed %rdi(tied-def 300) - %rax = COPY killed %rdi - RETQ killed %rax + INLINEASM &"$foo", 1, 2818058, def $rdi, 2147483657, killed $rdi(tied-def 300) + $rax = COPY killed $rdi + RETQ killed $rax ... diff --git a/llvm/test/CodeGen/MIR/X86/jump-table-info.mir b/llvm/test/CodeGen/MIR/X86/jump-table-info.mir index 71dd46b8218..ca0e992bdac 100644 --- a/llvm/test/CodeGen/MIR/X86/jump-table-info.mir +++ b/llvm/test/CodeGen/MIR/X86/jump-table-info.mir @@ -72,37 +72,37 @@ body: | bb.0.entry: successors: %bb.2, %bb.1 - %eax = MOV32rr %edi, implicit-def %rax - CMP32ri8 %edi, 3, implicit-def %eflags - JA_1 %bb.2, implicit %eflags + $eax = MOV32rr $edi, implicit-def $rax + CMP32ri8 $edi, 3, implicit-def $eflags + JA_1 %bb.2, implicit $eflags bb.1.entry: successors: %bb.3, %bb.4, %bb.5, %bb.6 - ; CHECK: %rcx = LEA64r %rip, 1, %noreg, %jump-table.0, %noreg - %rcx = LEA64r %rip, 1, _, %jump-table.0, _ - %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _ - %rax = ADD64rr %rax, %rcx, implicit-def %eflags - JMP64r %rax + ; CHECK: $rcx = LEA64r $rip, 1, $noreg, %jump-table.0, $noreg + $rcx = LEA64r $rip, 1, _, %jump-table.0, _ + $rax = MOVSX64rm32 $rcx, 4, $rax, 0, _ + $rax = ADD64rr $rax, $rcx, implicit-def $eflags + JMP64r $rax bb.2.def: - %eax = MOV32r0 implicit-def %eflags - RETQ %eax + $eax = MOV32r0 implicit-def $eflags + RETQ $eax bb.3.lbl1: - %eax = MOV32ri 1 - RETQ %eax + $eax = MOV32ri 1 + RETQ $eax bb.4.lbl2: - %eax = MOV32ri 2 - RETQ %eax + $eax = MOV32ri 2 + RETQ $eax bb.5.lbl3: - %eax = MOV32ri 4 - RETQ %eax + $eax = MOV32ri 4 + RETQ $eax bb.6.lbl4: - %eax = MOV32ri 8 - RETQ %eax + $eax = MOV32ri 8 + RETQ $eax ... --- name: test_jumptable2 @@ -115,36 +115,36 @@ body: | bb.0.entry: successors: %bb.2, %bb.1 - %eax = MOV32rr %edi, implicit-def %rax - CMP32ri8 %edi, 3, implicit-def %eflags - JA_1 %bb.2, implicit %eflags + $eax = MOV32rr $edi, implicit-def $rax + CMP32ri8 $edi, 3, implicit-def $eflags + JA_1 %bb.2, implicit $eflags bb.1.entry: successors: %bb.3, %bb.4, %bb.5, %bb.6 ; Verify that the printer will use an id of 0 for this jump table: - ; CHECK: %rcx = LEA64r %rip, 1, %noreg, %jump-table.0, %noreg - %rcx = LEA64r %rip, 1, _, %jump-table.1, _ - %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _ - %rax = ADD64rr %rax, %rcx, implicit-def %eflags - JMP64r %rax + ; CHECK: $rcx = LEA64r $rip, 1, $noreg, %jump-table.0, $noreg + $rcx = LEA64r $rip, 1, _, %jump-table.1, _ + $rax = MOVSX64rm32 $rcx, 4, $rax, 0, _ + $rax = ADD64rr $rax, $rcx, implicit-def $eflags + JMP64r $rax bb.2.def: - %eax = MOV32r0 implicit-def %eflags - RETQ %eax + $eax = MOV32r0 implicit-def $eflags + RETQ $eax bb.3.lbl1: - %eax = MOV32ri 1 - RETQ %eax + $eax = MOV32ri 1 + RETQ $eax bb.4.lbl2: - %eax = MOV32ri 2 - RETQ %eax + $eax = MOV32ri 2 + RETQ $eax bb.5.lbl3: - %eax = MOV32ri 4 - RETQ %eax + $eax = MOV32ri 4 + RETQ $eax bb.6.lbl4: - %eax = MOV32ri 8 - RETQ %eax + $eax = MOV32ri 8 + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir b/llvm/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir index 1eeabfba812..8c4d06bbe92 100644 --- a/llvm/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir +++ b/llvm/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir @@ -42,35 +42,35 @@ body: | bb.0.entry: successors: %bb.2.def, %bb.1.entry - %eax = MOV32rr %edi, implicit-def %rax - CMP32ri8 %edi, 3, implicit-def %eflags - JA_1 %bb.2.def, implicit %eflags + $eax = MOV32rr $edi, implicit-def $rax + CMP32ri8 $edi, 3, implicit-def $eflags + JA_1 %bb.2.def, implicit $eflags bb.1.entry: successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4 - %rcx = LEA64r %rip, 1, _, %jump-table.0, _ - %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _ - %rax = ADD64rr %rax, %rcx, implicit-def %eflags - JMP64r %rax + $rcx = LEA64r $rip, 1, _, %jump-table.0, _ + $rax = MOVSX64rm32 $rcx, 4, $rax, 0, _ + $rax = ADD64rr $rax, $rcx, implicit-def $eflags + JMP64r $rax bb.2.def: - %eax = MOV32r0 implicit-def %eflags - RETQ %eax + $eax = MOV32r0 implicit-def $eflags + RETQ $eax bb.3.lbl1: - %eax = MOV32ri 1 - RETQ %eax + $eax = MOV32ri 1 + RETQ $eax bb.4.lbl2: - %eax = MOV32ri 2 - RETQ %eax + $eax = MOV32ri 2 + RETQ $eax bb.5.lbl3: - %eax = MOV32ri 4 - RETQ %eax + $eax = MOV32ri 4 + RETQ $eax bb.6.lbl4: - %eax = MOV32ri 8 - RETQ %eax + $eax = MOV32ri 8 + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/killed-register-flag.mir b/llvm/test/CodeGen/MIR/X86/killed-register-flag.mir index 159553ba482..13d99d56529 100644 --- a/llvm/test/CodeGen/MIR/X86/killed-register-flag.mir +++ b/llvm/test/CodeGen/MIR/X86/killed-register-flag.mir @@ -23,18 +23,18 @@ body: | bb.0.entry: successors: %bb.1.less, %bb.2.exit - CMP32ri8 %edi, 10, implicit-def %eflags - JG_1 %bb.2.exit, implicit %eflags + CMP32ri8 $edi, 10, implicit-def $eflags + JG_1 %bb.2.exit, implicit $eflags bb.1.less: - ; CHECK: %eax = MOV32r0 - ; CHECK-NEXT: RETQ killed %eax - %eax = MOV32r0 implicit-def %eflags - RETQ killed %eax + ; CHECK: $eax = MOV32r0 + ; CHECK-NEXT: RETQ killed $eax + $eax = MOV32r0 implicit-def $eflags + RETQ killed $eax bb.2.exit: - ; CHECK: %eax = COPY killed %edi - ; CHECK-NEXT: RETQ killed %eax - %eax = COPY killed %edi - RETQ killed %eax + ; CHECK: $eax = COPY killed $edi + ; CHECK-NEXT: RETQ killed $eax + $eax = COPY killed $edi + RETQ killed $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir b/llvm/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir index 988a3432e79..c36a67670dc 100644 --- a/llvm/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir +++ b/llvm/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir @@ -18,10 +18,10 @@ stack: - { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 } body: | bb.0.entry: - %rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags + $rsp = SUB64ri32 $rsp, 4040, implicit-def dead $eflags ; CHECK: [[@LINE+1]]:36: expected a 32 bit integer (the cfi offset is too large) CFI_INSTRUCTION def_cfa_offset 123456789123456 - %rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags + $rsp = ADD64ri32 $rsp, 4040, implicit-def dead $eflags RETQ ... diff --git a/llvm/test/CodeGen/MIR/X86/large-immediate-operand-error.mir b/llvm/test/CodeGen/MIR/X86/large-immediate-operand-error.mir index 0d72690401d..a59527230f4 100644 --- a/llvm/test/CodeGen/MIR/X86/large-immediate-operand-error.mir +++ b/llvm/test/CodeGen/MIR/X86/large-immediate-operand-error.mir @@ -13,6 +13,6 @@ name: foo body: | bb.0.entry: ; CHECK: [[@LINE+1]]:20: integer literal is too large to be an immediate operand - %eax = MOV32ri 12346127502983478823754212949184914 - RETQ %eax + $eax = MOV32ri 12346127502983478823754212949184914 + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/large-index-number-error.mir b/llvm/test/CodeGen/MIR/X86/large-index-number-error.mir index f8423fd43e1..f47b5980391 100644 --- a/llvm/test/CodeGen/MIR/X86/large-index-number-error.mir +++ b/llvm/test/CodeGen/MIR/X86/large-index-number-error.mir @@ -20,14 +20,14 @@ name: foo body: | bb.0.entry: - %eax = MOV32rm %rdi, 1, _, 0, _ - CMP32ri8 %eax, 10, implicit-def %eflags + $eax = MOV32rm $rdi, 1, _, 0, _ + CMP32ri8 $eax, 10, implicit-def $eflags ; CHECK: [[@LINE+1]]:10: expected 32-bit integer (too large) - JG_1 %bb.123456789123456, implicit %eflags + JG_1 %bb.123456789123456, implicit $eflags bb.1: - %eax = MOV32r0 implicit-def %eflags + $eax = MOV32r0 implicit-def $eflags bb.2: - RETQ %eax + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/large-offset-number-error.mir b/llvm/test/CodeGen/MIR/X86/large-offset-number-error.mir index 0b2225f1541..0c0f5d87b2e 100644 --- a/llvm/test/CodeGen/MIR/X86/large-offset-number-error.mir +++ b/llvm/test/CodeGen/MIR/X86/large-offset-number-error.mir @@ -17,8 +17,8 @@ name: inc body: | bb.0.entry: ; CHECK: [[@LINE+1]]:37: expected 64-bit integer (too large) - %rax = MOV64rm %rip, 1, _, @G + 123456789123456789123456789, _ - %eax = MOV32rm %rax, 1, _, 0, _ - %eax = INC32r %eax implicit-def %eflags - RETQ %eax + $rax = MOV64rm $rip, 1, _, @G + 123456789123456789123456789, _ + $eax = MOV32rm $rax, 1, _, 0, _ + $eax = INC32r $eax implicit-def $eflags + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir b/llvm/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir index 616adfad1ed..59bd717aead 100644 --- a/llvm/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir +++ b/llvm/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir @@ -13,12 +13,12 @@ name: test tracksRegLiveness: true liveins: - - { reg: '%rdi' } + - { reg: '$rdi' } body: | bb.0.entry: - liveins: %rdi + liveins: $rdi ; CHECK: [[@LINE+1]]:53: expected 64-bit integer (too large) - %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 12345678912345678924218574857 from %ir.a) - RETQ %eax + $eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load 12345678912345678924218574857 from %ir.a) + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/liveout-register-mask.mir b/llvm/test/CodeGen/MIR/X86/liveout-register-mask.mir index 3e38348961f..6db52cdaee0 100644 --- a/llvm/test/CodeGen/MIR/X86/liveout-register-mask.mir +++ b/llvm/test/CodeGen/MIR/X86/liveout-register-mask.mir @@ -17,8 +17,8 @@ name: small_patchpoint_codegen tracksRegLiveness: true liveins: - - { reg: '%rdi' } - - { reg: '%rsi' } + - { reg: '$rdi' } + - { reg: '$rsi' } frameInfo: hasPatchPoint: true stackSize: 8 @@ -28,15 +28,15 @@ fixedStack: - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 } body: | bb.0.entry: - liveins: %rdi, %rsi, %rbp + liveins: $rdi, $rsi, $rbp - frame-setup PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp + frame-setup PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp CFI_INSTRUCTION def_cfa_offset 16 - CFI_INSTRUCTION offset %rbp, -16 - %rbp = frame-setup MOV64rr %rsp - CFI_INSTRUCTION def_cfa_register %rbp - ; CHECK: PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, liveout(%esp, %rsp, %sp, %spl), - PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, liveout(%esp, %rsp, %sp, %spl), implicit-def dead early-clobber %r11, implicit-def %rsp, implicit-def dead %rax - %rbp = POP64r implicit-def %rsp, implicit %rsp + CFI_INSTRUCTION offset $rbp, -16 + $rbp = frame-setup MOV64rr $rsp + CFI_INSTRUCTION def_cfa_register $rbp + ; CHECK: PATCHPOINT 5, 5, 0, 2, 0, $rdi, $rsi, csr_64, liveout($esp, $rsp, $sp, $spl), + PATCHPOINT 5, 5, 0, 2, 0, $rdi, $rsi, csr_64, liveout($esp, $rsp, $sp, $spl), implicit-def dead early-clobber $r11, implicit-def $rsp, implicit-def dead $rax + $rbp = POP64r implicit-def $rsp, implicit $rsp RETQ ... diff --git a/llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir b/llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir index a7866f239be..6fa01aa76d8 100644 --- a/llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir @@ -38,18 +38,18 @@ body: | bb.0.entry: successors: %bb.1, %bb.2 - %eax = MOV32rm %rdi, 1, _, 0, _ - ; CHECK: CMP32ri8 %eax, 10 + $eax = MOV32rm $rdi, 1, _, 0, _ + ; CHECK: CMP32ri8 $eax, 10 ; CHECK-NEXT: JG_1 %bb.2 - CMP32ri8 %eax, 10, implicit-def %eflags - JG_1 %bb.2, implicit %eflags + CMP32ri8 $eax, 10, implicit-def $eflags + JG_1 %bb.2, implicit $eflags ; CHECK: bb.1.less: bb.1.less: - %eax = MOV32r0 implicit-def %eflags + $eax = MOV32r0 implicit-def $eflags bb.2.exit: - RETQ %eax + RETQ $eax ... --- # CHECK: name: bar @@ -59,15 +59,15 @@ body: | bb.0.entry: successors: %bb.1, %bb.3 - %eax = MOV32rm %rdi, 1, _, 0, _ - ; CHECK: CMP32ri8 %eax, 10 + $eax = MOV32rm $rdi, 1, _, 0, _ + ; CHECK: CMP32ri8 $eax, 10 ; CHECK-NEXT: JG_1 %bb.2 - CMP32ri8 %eax, 10, implicit-def %eflags - JG_1 %bb.3, implicit %eflags + CMP32ri8 $eax, 10, implicit-def $eflags + JG_1 %bb.3, implicit $eflags bb.1: - %eax = MOV32r0 implicit-def %eflags + $eax = MOV32r0 implicit-def $eflags bb.3: - RETQ %eax + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/machine-instructions.mir b/llvm/test/CodeGen/MIR/X86/machine-instructions.mir index 28d4d47e3e7..1989ee35fb5 100644 --- a/llvm/test/CodeGen/MIR/X86/machine-instructions.mir +++ b/llvm/test/CodeGen/MIR/X86/machine-instructions.mir @@ -18,6 +18,6 @@ body: | bb.0.entry: ; CHECK: MOV32rr ; CHECK-NEXT: RETQ - %eax = MOV32rr %eax - RETQ %eax + $eax = MOV32rr $eax + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/machine-verifier.mir b/llvm/test/CodeGen/MIR/X86/machine-verifier.mir index 7421146c22e..16a55ea5fea 100644 --- a/llvm/test/CodeGen/MIR/X86/machine-verifier.mir +++ b/llvm/test/CodeGen/MIR/X86/machine-verifier.mir @@ -14,7 +14,7 @@ name: inc tracksRegLiveness: true body: | bb.0.entry: - liveins: %edi + liveins: $edi ; CHECK: *** Bad machine code: Too few operands *** ; CHECK: instruction: COPY ; CHECK: 2 operands expected, but 0 given. diff --git a/llvm/test/CodeGen/MIR/X86/memory-operands.mir b/llvm/test/CodeGen/MIR/X86/memory-operands.mir index 3d23b47b6c7..85e31c09d1c 100644 --- a/llvm/test/CodeGen/MIR/X86/memory-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/memory-operands.mir @@ -194,151 +194,151 @@ name: test tracksRegLiveness: true liveins: - - { reg: '%rdi' } + - { reg: '$rdi' } body: | bb.0.entry: - liveins: %rdi - ; CHECK: %eax = MOV32rm %rdi, 1, %noreg, 0, %noreg :: (load 4 from %ir.a) - ; CHECK-NEXT: MOV32mi killed %rdi, 1, %noreg, 0, %noreg, 42 :: (store 4 into %ir.a) - %eax = MOV32rm %rdi, 1, _, 0, _ :: (load 4 from %ir.a) - MOV32mi killed %rdi, 1, _, 0, _, 42 :: (store 4 into %ir.a) - RETQ %eax + liveins: $rdi + ; CHECK: $eax = MOV32rm $rdi, 1, $noreg, 0, $noreg :: (load 4 from %ir.a) + ; CHECK-NEXT: MOV32mi killed $rdi, 1, $noreg, 0, $noreg, 42 :: (store 4 into %ir.a) + $eax = MOV32rm $rdi, 1, _, 0, _ :: (load 4 from %ir.a) + MOV32mi killed $rdi, 1, _, 0, _, 42 :: (store 4 into %ir.a) + RETQ $eax ... --- name: test2 tracksRegLiveness: true liveins: - - { reg: '%rdi' } + - { reg: '$rdi' } body: | bb.0.entry2: - liveins: %rdi - ; CHECK: INC32m killed %rdi, 1, %noreg, 0, %noreg, implicit-def dead %eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value") - INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value") + liveins: $rdi + ; CHECK: INC32m killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value") + INC32m killed $rdi, 1, _, 0, _, implicit-def dead $eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value") RETQ ... --- name: test3 tracksRegLiveness: true liveins: - - { reg: '%rdi' } + - { reg: '$rdi' } frameInfo: maxAlignment: 4 stack: - { id: 0, offset: -12, size: 4, alignment: 4 } body: | bb.0.entry3: - liveins: %rdi + liveins: $rdi ; Verify that the unnamed local values can be serialized. ; CHECK-LABEL: name: test3 - ; CHECK: %eax = MOV32rm killed %rdi, 1, %noreg, 0, %noreg :: (load 4 from %ir.0) - ; CHECK: MOV32mr %rsp, 1, %noreg, -4, %noreg, killed %eax :: (store 4 into %ir.1) - %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.0) - %eax = INC32r killed %eax, implicit-def dead %eflags - MOV32mr %rsp, 1, _, -4, _, killed %eax :: (store 4 into %ir.1) + ; CHECK: $eax = MOV32rm killed $rdi, 1, $noreg, 0, $noreg :: (load 4 from %ir.0) + ; CHECK: MOV32mr $rsp, 1, $noreg, -4, $noreg, killed $eax :: (store 4 into %ir.1) + $eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load 4 from %ir.0) + $eax = INC32r killed $eax, implicit-def dead $eflags + MOV32mr $rsp, 1, _, -4, _, killed $eax :: (store 4 into %ir.1) RETQ ... --- name: volatile_inc tracksRegLiveness: true liveins: - - { reg: '%rdi' } + - { reg: '$rdi' } body: | bb.0.entry: - liveins: %rdi + liveins: $rdi ; CHECK: name: volatile_inc - ; CHECK: %eax = MOV32rm %rdi, 1, %noreg, 0, %noreg :: (volatile load 4 from %ir.x) - ; CHECK: MOV32mr killed %rdi, 1, %noreg, 0, %noreg, %eax :: (volatile store 4 into %ir.x) - %eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile load 4 from %ir.x) - %eax = INC32r killed %eax, implicit-def dead %eflags - MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x) - RETQ %eax + ; CHECK: $eax = MOV32rm $rdi, 1, $noreg, 0, $noreg :: (volatile load 4 from %ir.x) + ; CHECK: MOV32mr killed $rdi, 1, $noreg, 0, $noreg, $eax :: (volatile store 4 into %ir.x) + $eax = MOV32rm $rdi, 1, _, 0, _ :: (volatile load 4 from %ir.x) + $eax = INC32r killed $eax, implicit-def dead $eflags + MOV32mr killed $rdi, 1, _, 0, _, $eax :: (volatile store 4 into %ir.x) + RETQ $eax ... --- name: non_temporal_store tracksRegLiveness: true liveins: - - { reg: '%rdi' } - - { reg: '%esi' } + - { reg: '$rdi' } + - { reg: '$esi' } body: | bb.0.entry: - liveins: %esi, %rdi + liveins: $esi, $rdi ; CHECK: name: non_temporal_store - ; CHECK: MOVNTImr killed %rdi, 1, %noreg, 0, %noreg, killed %esi :: (non-temporal store 4 into %ir.a) - MOVNTImr killed %rdi, 1, _, 0, _, killed %esi :: (non-temporal store 4 into %ir.a) + ; CHECK: MOVNTImr killed $rdi, 1, $noreg, 0, $noreg, killed $esi :: (non-temporal store 4 into %ir.a) + MOVNTImr killed $rdi, 1, _, 0, _, killed $esi :: (non-temporal store 4 into %ir.a) RETQ ... --- name: invariant_load tracksRegLiveness: true liveins: - - { reg: '%rdi' } + - { reg: '$rdi' } body: | bb.0.entry: - liveins: %rdi + liveins: $rdi ; CHECK: name: invariant_load - ; CHECK: %eax = MOV32rm killed %rdi, 1, %noreg, 0, %noreg :: (invariant load 4 from %ir.x) - %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (invariant load 4 from %ir.x) - RETQ %eax + ; CHECK: $eax = MOV32rm killed $rdi, 1, $noreg, 0, $noreg :: (invariant load 4 from %ir.x) + $eax = MOV32rm killed $rdi, 1, _, 0, _ :: (invariant load 4 from %ir.x) + RETQ $eax ... --- name: memory_offset tracksRegLiveness: true liveins: - - { reg: '%rdi' } + - { reg: '$rdi' } body: | bb.0.entry: - liveins: %rdi + liveins: $rdi ; CHECK: name: memory_offset - ; CHECK: %xmm0 = MOVAPSrm %rdi, 1, %noreg, 0, %noreg :: (load 16 from %ir.vec) - ; CHECK-NEXT: %xmm1 = MOVAPSrm %rdi, 1, %noreg, 16, %noreg :: (load 16 from %ir.vec + 16) - ; CHECK: MOVAPSmr %rdi, 1, %noreg, 0, %noreg, killed %xmm0 :: (store 16 into %ir.vec) - ; CHECK-NEXT: MOVAPSmr killed %rdi, 1, %noreg, 16, %noreg, killed %xmm1 :: (store 16 into %ir.vec + 16) - %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec) - %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16) - %xmm2 = FsFLD0SS - %xmm1 = MOVSSrr killed %xmm1, killed %xmm2 - MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec) - MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16) + ; CHECK: $xmm0 = MOVAPSrm $rdi, 1, $noreg, 0, $noreg :: (load 16 from %ir.vec) + ; CHECK-NEXT: $xmm1 = MOVAPSrm $rdi, 1, $noreg, 16, $noreg :: (load 16 from %ir.vec + 16) + ; CHECK: MOVAPSmr $rdi, 1, $noreg, 0, $noreg, killed $xmm0 :: (store 16 into %ir.vec) + ; CHECK-NEXT: MOVAPSmr killed $rdi, 1, $noreg, 16, $noreg, killed $xmm1 :: (store 16 into %ir.vec + 16) + $xmm0 = MOVAPSrm $rdi, 1, _, 0, _ :: (load 16 from %ir.vec) + $xmm1 = MOVAPSrm $rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16) + $xmm2 = FsFLD0SS + $xmm1 = MOVSSrr killed $xmm1, killed $xmm2 + MOVAPSmr $rdi, 1, _, 0, _, killed $xmm0 :: (store 16 into %ir.vec) + MOVAPSmr killed $rdi, 1, _, 16, _, killed $xmm1 :: (store 16 into %ir.vec + 16) RETQ ... --- name: memory_alignment tracksRegLiveness: true liveins: - - { reg: '%rdi' } + - { reg: '$rdi' } body: | bb.0.entry: - liveins: %rdi + liveins: $rdi ; CHECK: name: memory_alignment - ; CHECK: %xmm0 = MOVAPSrm %rdi, 1, %noreg, 0, %noreg :: (load 16 from %ir.vec, align 32) - ; CHECK-NEXT: %xmm1 = MOVAPSrm %rdi, 1, %noreg, 16, %noreg :: (load 16 from %ir.vec + 16, align 32) - ; CHECK: MOVAPSmr %rdi, 1, %noreg, 0, %noreg, killed %xmm0 :: (store 16 into %ir.vec, align 32) - ; CHECK-NEXT: MOVAPSmr killed %rdi, 1, %noreg, 16, %noreg, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32) - %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align 32) - %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32) - %xmm2 = FsFLD0SS - %xmm1 = MOVSSrr killed %xmm1, killed %xmm2 - MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32) - MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32) + ; CHECK: $xmm0 = MOVAPSrm $rdi, 1, $noreg, 0, $noreg :: (load 16 from %ir.vec, align 32) + ; CHECK-NEXT: $xmm1 = MOVAPSrm $rdi, 1, $noreg, 16, $noreg :: (load 16 from %ir.vec + 16, align 32) + ; CHECK: MOVAPSmr $rdi, 1, $noreg, 0, $noreg, killed $xmm0 :: (store 16 into %ir.vec, align 32) + ; CHECK-NEXT: MOVAPSmr killed $rdi, 1, $noreg, 16, $noreg, killed $xmm1 :: (store 16 into %ir.vec + 16, align 32) + $xmm0 = MOVAPSrm $rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align 32) + $xmm1 = MOVAPSrm $rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32) + $xmm2 = FsFLD0SS + $xmm1 = MOVSSrr killed $xmm1, killed $xmm2 + MOVAPSmr $rdi, 1, _, 0, _, killed $xmm0 :: (store 16 into %ir.vec, align 32) + MOVAPSmr killed $rdi, 1, _, 16, _, killed $xmm1 :: (store 16 into %ir.vec + 16, align 32) RETQ ... --- name: constant_pool_psv tracksRegLiveness: true liveins: - - { reg: '%xmm0' } + - { reg: '$xmm0' } constants: - id: 0 value: 'double 3.250000e+00' body: | bb.0.entry: - liveins: %xmm0 + liveins: $xmm0 ; CHECK: name: constant_pool_psv - ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.0, %noreg :: (load 8 from constant-pool) - ; CHECK-NEXT: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.0, %noreg :: (load 8 from constant-pool + 8) - %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool) - %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool + 8) - RETQ %xmm0 + ; CHECK: $xmm0 = ADDSDrm killed $xmm0, $rip, 1, $noreg, %const.0, $noreg :: (load 8 from constant-pool) + ; CHECK-NEXT: $xmm0 = ADDSDrm killed $xmm0, $rip, 1, $noreg, %const.0, $noreg :: (load 8 from constant-pool + 8) + $xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.0, _ :: (load 8 from constant-pool) + $xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.0, _ :: (load 8 from constant-pool + 8) + RETQ $xmm0 ... --- name: stack_psv @@ -353,14 +353,14 @@ fixedStack: - { id: 0, offset: 0, size: 10, alignment: 16, isImmutable: true, isAliased: false } body: | bb.0.entry: - %rsp = frame-setup SUB64ri8 %rsp, 24, implicit-def dead %eflags + $rsp = frame-setup SUB64ri8 $rsp, 24, implicit-def dead $eflags CFI_INSTRUCTION def_cfa_offset 32 - LD_F80m %rsp, 1, %noreg, 32, %noreg, implicit-def dead %fpsw + LD_F80m $rsp, 1, $noreg, 32, $noreg, implicit-def dead $fpsw ; CHECK: name: stack_psv - ; CHECK: ST_FP80m %rsp, 1, %noreg, 0, %noreg, implicit-def dead %fpsw :: (store 10 into stack, align 16) - ST_FP80m %rsp, 1, _, 0, _, implicit-def dead %fpsw :: (store 10 into stack, align 16) - CALL64pcrel32 &cosl, csr_64, implicit %rsp, implicit-def %rsp, implicit-def %fp0 - %rsp = ADD64ri8 %rsp, 24, implicit-def dead %eflags + ; CHECK: ST_FP80m $rsp, 1, $noreg, 0, $noreg, implicit-def dead $fpsw :: (store 10 into stack, align 16) + ST_FP80m $rsp, 1, _, 0, _, implicit-def dead $fpsw :: (store 10 into stack, align 16) + CALL64pcrel32 &cosl, csr_64, implicit $rsp, implicit-def $rsp, implicit-def $fp0 + $rsp = ADD64ri8 $rsp, 24, implicit-def dead $eflags RETQ ... --- @@ -369,32 +369,32 @@ tracksRegLiveness: true body: | bb.0.entry: ; CHECK: name: got_psv - ; CHECK: %rax = MOV64rm %rip, 1, %noreg, @G, %noreg :: (load 8 from got) - %rax = MOV64rm %rip, 1, _, @G, _ :: (load 8 from got) - %eax = MOV32rm killed %rax, 1, _, 0, _ - %eax = INC32r killed %eax, implicit-def dead %eflags - RETQ %eax + ; CHECK: $rax = MOV64rm $rip, 1, $noreg, @G, $noreg :: (load 8 from got) + $rax = MOV64rm $rip, 1, _, @G, _ :: (load 8 from got) + $eax = MOV32rm killed $rax, 1, _, 0, _ + $eax = INC32r killed $eax, implicit-def dead $eflags + RETQ $eax ... --- name: global_value tracksRegLiveness: true body: | bb.0.entry: - %rax = MOV64rm %rip, 1, _, @G, _ + $rax = MOV64rm $rip, 1, _, @G, _ ; CHECK-LABEL: name: global_value - ; CHECK: %eax = MOV32rm killed %rax, 1, %noreg, 0, %noreg, implicit-def %rax :: (load 4 from @G) - ; CHECK: %ecx = MOV32rm killed %rcx, 1, %noreg, 0, %noreg, implicit-def %rcx :: (load 4 from @0) - %eax = MOV32rm killed %rax, 1, _, 0, _, implicit-def %rax :: (load 4 from @G) - %rcx = MOV64rm %rip, 1, _, @0, _ - %ecx = MOV32rm killed %rcx, 1, _, 0, _, implicit-def %rcx :: (load 4 from @0) - %eax = LEA64_32r killed %rax, 1, killed %rcx, 1, _ - RETQ %eax + ; CHECK: $eax = MOV32rm killed $rax, 1, $noreg, 0, $noreg, implicit-def $rax :: (load 4 from @G) + ; CHECK: $ecx = MOV32rm killed $rcx, 1, $noreg, 0, $noreg, implicit-def $rcx :: (load 4 from @0) + $eax = MOV32rm killed $rax, 1, _, 0, _, implicit-def $rax :: (load 4 from @G) + $rcx = MOV64rm $rip, 1, _, @0, _ + $ecx = MOV32rm killed $rcx, 1, _, 0, _, implicit-def $rcx :: (load 4 from @0) + $eax = LEA64_32r killed $rax, 1, killed $rcx, 1, _ + RETQ $eax ... --- name: jumptable_psv tracksRegLiveness: true liveins: - - { reg: '%edi' } + - { reg: '$edi' } jumpTable: kind: label-difference32 entries: @@ -403,100 +403,100 @@ jumpTable: body: | bb.0.entry: successors: %bb.2.def, %bb.1.entry - liveins: %edi + liveins: $edi - %eax = MOV32rr %edi, implicit-def %rax - CMP32ri8 killed %edi, 3, implicit-def %eflags - JA_1 %bb.2.def, implicit killed %eflags + $eax = MOV32rr $edi, implicit-def $rax + CMP32ri8 killed $edi, 3, implicit-def $eflags + JA_1 %bb.2.def, implicit killed $eflags bb.1.entry: successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4 - liveins: %rax + liveins: $rax - %rcx = LEA64r %rip, 1, _, %jump-table.0, _ + $rcx = LEA64r $rip, 1, _, %jump-table.0, _ ; CHECK: name: jumptable_psv - ; CHECK: %rax = MOVSX64rm32 %rcx, 4, killed %rax, 0, %noreg :: (load 4 from jump-table, align 8) - %rax = MOVSX64rm32 %rcx, 4, killed %rax, 0, _ :: (load 4 from jump-table, align 8) - %rax = ADD64rr killed %rax, killed %rcx, implicit-def dead %eflags - JMP64r killed %rax + ; CHECK: $rax = MOVSX64rm32 $rcx, 4, killed $rax, 0, $noreg :: (load 4 from jump-table, align 8) + $rax = MOVSX64rm32 $rcx, 4, killed $rax, 0, _ :: (load 4 from jump-table, align 8) + $rax = ADD64rr killed $rax, killed $rcx, implicit-def dead $eflags + JMP64r killed $rax bb.2.def: - %eax = MOV32r0 implicit-def dead %eflags - RETQ %eax + $eax = MOV32r0 implicit-def dead $eflags + RETQ $eax bb.3.lbl1: - %eax = MOV32ri 1 - RETQ %eax + $eax = MOV32ri 1 + RETQ $eax bb.4.lbl2: - %eax = MOV32ri 2 - RETQ %eax + $eax = MOV32ri 2 + RETQ $eax bb.5.lbl3: - %eax = MOV32ri 4 - RETQ %eax + $eax = MOV32ri 4 + RETQ $eax bb.6.lbl4: - %eax = MOV32ri 8 - RETQ %eax + $eax = MOV32ri 8 + RETQ $eax ... --- name: tbaa_metadata tracksRegLiveness: true body: | bb.0.entry: - %rax = MOV64rm %rip, 1, _, @a, _ :: (load 8 from got) + $rax = MOV64rm $rip, 1, _, @a, _ :: (load 8 from got) ; CHECK-LABEL: name: tbaa_metadata - ; CHECK: %eax = MOV32rm killed %rax, 1, %noreg, 0, %noreg, implicit-def %rax :: (load 4 from @a, !tbaa !2) - ; CHECK-NEXT: %eax = MOV32rm killed %rax, 1, %noreg, 0, %noreg :: (load 4 from %ir.total_len2, !tbaa !6) - %eax = MOV32rm killed %rax, 1, _, 0, _, implicit-def %rax :: (load 4 from @a, !tbaa !2) - %eax = MOV32rm killed %rax, 1, _, 0, _ :: (load 4 from %ir.total_len2, !tbaa !6) - RETQ %eax + ; CHECK: $eax = MOV32rm killed $rax, 1, $noreg, 0, $noreg, implicit-def $rax :: (load 4 from @a, !tbaa !2) + ; CHECK-NEXT: $eax = MOV32rm killed $rax, 1, $noreg, 0, $noreg :: (load 4 from %ir.total_len2, !tbaa !6) + $eax = MOV32rm killed $rax, 1, _, 0, _, implicit-def $rax :: (load 4 from @a, !tbaa !2) + $eax = MOV32rm killed $rax, 1, _, 0, _ :: (load 4 from %ir.total_len2, !tbaa !6) + RETQ $eax ... --- name: aa_scope tracksRegLiveness: true liveins: - - { reg: '%rdi' } - - { reg: '%rsi' } + - { reg: '$rdi' } + - { reg: '$rsi' } body: | bb.0.entry: - liveins: %rdi, %rsi + liveins: $rdi, $rsi ; CHECK-LABEL: name: aa_scope - ; CHECK: %xmm0 = MOVSSrm %rsi, 1, %noreg, 0, %noreg :: (load 4 from %ir.c, !alias.scope !9) - %xmm0 = MOVSSrm %rsi, 1, _, 0, _ :: (load 4 from %ir.c, !alias.scope !9) - ; CHECK-NEXT: MOVSSmr %rdi, 1, %noreg, 20, %noreg, killed %xmm0 :: (store 4 into %ir.arrayidx.i, !noalias !9) - MOVSSmr %rdi, 1, _, 20, _, killed %xmm0 :: (store 4 into %ir.arrayidx.i, !noalias !9) - %xmm0 = MOVSSrm killed %rsi, 1, _, 0, _ :: (load 4 from %ir.c) - MOVSSmr killed %rdi, 1, _, 28, _, killed %xmm0 :: (store 4 into %ir.arrayidx) + ; CHECK: $xmm0 = MOVSSrm $rsi, 1, $noreg, 0, $noreg :: (load 4 from %ir.c, !alias.scope !9) + $xmm0 = MOVSSrm $rsi, 1, _, 0, _ :: (load 4 from %ir.c, !alias.scope !9) + ; CHECK-NEXT: MOVSSmr $rdi, 1, $noreg, 20, $noreg, killed $xmm0 :: (store 4 into %ir.arrayidx.i, !noalias !9) + MOVSSmr $rdi, 1, _, 20, _, killed $xmm0 :: (store 4 into %ir.arrayidx.i, !noalias !9) + $xmm0 = MOVSSrm killed $rsi, 1, _, 0, _ :: (load 4 from %ir.c) + MOVSSmr killed $rdi, 1, _, 28, _, killed $xmm0 :: (store 4 into %ir.arrayidx) RETQ ... --- name: range_metadata tracksRegLiveness: true liveins: - - { reg: '%rdi' } + - { reg: '$rdi' } body: | bb.0.entry: - liveins: %rdi + liveins: $rdi ; CHECK-LABEL: name: range_metadata - ; CHECK: %al = MOV8rm killed %rdi, 1, %noreg, 0, %noreg :: (load 1 from %ir.x, !range !11) - %al = MOV8rm killed %rdi, 1, _, 0, _ :: (load 1 from %ir.x, !range !11) - RETQ %al + ; CHECK: $al = MOV8rm killed $rdi, 1, $noreg, 0, $noreg :: (load 1 from %ir.x, !range !11) + $al = MOV8rm killed $rdi, 1, _, 0, _ :: (load 1 from %ir.x, !range !11) + RETQ $al ... --- name: gep_value tracksRegLiveness: true liveins: - - { reg: '%rdi' } + - { reg: '$rdi' } body: | bb.0.entry: - liveins: %rdi + liveins: $rdi - %rax = MOV64rm %rip, 1, _, @values, _ :: (load 8 from got) + $rax = MOV64rm $rip, 1, _, @values, _ :: (load 8 from got) ; CHECK-LABEL: gep_value - ; CHECK: MOV32mr killed %rax, 1, %noreg, 0, %noreg, %edi, implicit killed %rdi :: (store 4 into `i32* getelementptr inbounds ([50 x %st], [50 x %st]* @values, i64 0, i64 0, i32 0)`, align 16) - MOV32mr killed %rax, 1, _, 0, _, %edi, implicit killed %rdi :: (store 4 into `i32* getelementptr inbounds ([50 x %st], [50 x %st]* @values, i64 0, i64 0, i32 0)`, align 16) + ; CHECK: MOV32mr killed $rax, 1, $noreg, 0, $noreg, $edi, implicit killed $rdi :: (store 4 into `i32* getelementptr inbounds ([50 x %st], [50 x %st]* @values, i64 0, i64 0, i32 0)`, align 16) + MOV32mr killed $rax, 1, _, 0, _, $edi, implicit killed $rdi :: (store 4 into `i32* getelementptr inbounds ([50 x %st], [50 x %st]* @values, i64 0, i64 0, i32 0)`, align 16) RETQ ... --- @@ -505,32 +505,32 @@ tracksRegLiveness: true body: | bb.0.entry: ; CHECK-LABEL: name: undef_value - ; CHECK: %rax = MOV64rm undef %rax, 1, %noreg, 0, %noreg :: (load 8 from `i8** undef`) - %rax = MOV64rm undef %rax, 1, _, 0, _ :: (load 8 from `i8** undef`) - RETQ %rax + ; CHECK: $rax = MOV64rm undef $rax, 1, $noreg, 0, $noreg :: (load 8 from `i8** undef`) + $rax = MOV64rm undef $rax, 1, _, 0, _ :: (load 8 from `i8** undef`) + RETQ $rax ... --- # Test memory operand without associated value. # CHECK-LABEL: name: dummy0 -# CHECK: %rax = MOV64rm undef %rax, 1, %noreg, 0, %noreg :: (load 8) +# CHECK: $rax = MOV64rm undef $rax, 1, $noreg, 0, $noreg :: (load 8) name: dummy0 tracksRegLiveness: true body: | bb.0: - %rax = MOV64rm undef %rax, 1, _, 0, _ :: (load 8) - RETQ %rax + $rax = MOV64rm undef $rax, 1, _, 0, _ :: (load 8) + RETQ $rax ... --- # Test parsing of stack references in machine memory operands. # CHECK-LABEL: name: dummy1 -# CHECK: %rax = MOV64rm %rsp, 1, %noreg, 0, %noreg :: (load 8 from %stack.0) +# CHECK: $rax = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load 8 from %stack.0) name: dummy1 tracksRegLiveness: true stack: - { id: 0, size: 4, alignment: 4 } body: | bb.0: - %rax = MOV64rm %rsp, 1, _, 0, _ :: (load 8 from %stack.0) - RETQ %rax + $rax = MOV64rm $rsp, 1, _, 0, _ :: (load 8 from %stack.0) + RETQ $rax ... diff --git a/llvm/test/CodeGen/MIR/X86/metadata-operands.mir b/llvm/test/CodeGen/MIR/X86/metadata-operands.mir index 94091cdb827..285b2a29b02 100644 --- a/llvm/test/CodeGen/MIR/X86/metadata-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/metadata-operands.mir @@ -49,12 +49,12 @@ stack: - { id: 0, name: x.addr, size: 4, alignment: 4 } body: | bb.0.entry: - liveins: %edi - ; CHECK: %0:gr32 = COPY %edi - ; CHECK-NEXT: DBG_VALUE %noreg, 0, !11, !DIExpression() - %0 = COPY %edi + liveins: $edi + ; CHECK: %0:gr32 = COPY $edi + ; CHECK-NEXT: DBG_VALUE $noreg, 0, !11, !DIExpression() + %0 = COPY $edi DBG_VALUE _, 0, !12, !DIExpression() MOV32mr %stack.0.x.addr, 1, _, 0, _, %0 - %eax = COPY %0 - RETQ %eax + $eax = COPY %0 + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/missing-closing-quote.mir b/llvm/test/CodeGen/MIR/X86/missing-closing-quote.mir index 0e912f5ea78..22f8ede90ba 100644 --- a/llvm/test/CodeGen/MIR/X86/missing-closing-quote.mir +++ b/llvm/test/CodeGen/MIR/X86/missing-closing-quote.mir @@ -16,7 +16,7 @@ name: test body: | bb.0.entry: ; CHECK: [[@LINE+1]]:48: end of machine instruction reached before the closing '"' - %rax = MOV64rm %rip, 1, _, @"quoted name, _ - %eax = MOV32rm killed %rax, 1, _, 0, _ - RETQ %eax + $rax = MOV64rm $rip, 1, _, @"quoted name, _ + $eax = MOV32rm killed $rax, 1, _, 0, _ + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/missing-comma.mir b/llvm/test/CodeGen/MIR/X86/missing-comma.mir index 0aaba6ddaa3..c87f5e476df 100644 --- a/llvm/test/CodeGen/MIR/X86/missing-comma.mir +++ b/llvm/test/CodeGen/MIR/X86/missing-comma.mir @@ -13,7 +13,7 @@ name: foo body: | bb.0.entry: ; CHECK: [[@LINE+1]]:25: expected ',' before the next machine operand - %eax = XOR32rr %eax %eflags - RETQ %eax + $eax = XOR32rr $eax $eflags + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/missing-implicit-operand.mir b/llvm/test/CodeGen/MIR/X86/missing-implicit-operand.mir index fd26f19d184..4961702bad2 100644 --- a/llvm/test/CodeGen/MIR/X86/missing-implicit-operand.mir +++ b/llvm/test/CodeGen/MIR/X86/missing-implicit-operand.mir @@ -25,14 +25,14 @@ body: | bb.0.entry: successors: %bb.1.less, %bb.2.exit - %eax = MOV32rm %rdi, 1, _, 0, _ - CMP32ri8 %eax, 10, implicit-def %eflags + $eax = MOV32rm $rdi, 1, _, 0, _ + CMP32ri8 $eax, 10, implicit-def $eflags ; CHECK: [[@LINE+1]]:20: missing implicit register operand 'implicit %eflags' JG_1 %bb.2.exit bb.1.less: - %eax = MOV32r0 implicit-def %eflags + $eax = MOV32r0 implicit-def $eflags bb.2.exit: - RETQ %eax + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/named-registers.mir b/llvm/test/CodeGen/MIR/X86/named-registers.mir index eedc2dbe853..1bb67225d38 100644 --- a/llvm/test/CodeGen/MIR/X86/named-registers.mir +++ b/llvm/test/CodeGen/MIR/X86/named-registers.mir @@ -14,8 +14,8 @@ name: foo body: | bb.0.entry: - ; CHECK: %eax = MOV32r0 - ; CHECK-NEXT: RETQ %eax - %eax = MOV32r0 implicit-def %eflags - RETQ %eax + ; CHECK: $eax = MOV32r0 + ; CHECK-NEXT: RETQ $eax + $eax = MOV32r0 implicit-def $eflags + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/newline-handling.mir b/llvm/test/CodeGen/MIR/X86/newline-handling.mir index 1a93c1a6425..d25a49f4c1c 100644 --- a/llvm/test/CodeGen/MIR/X86/newline-handling.mir +++ b/llvm/test/CodeGen/MIR/X86/newline-handling.mir @@ -31,79 +31,79 @@ name: foo tracksRegLiveness: true liveins: - - { reg: '%edi' } + - { reg: '$edi' } # CHECK-LABEL: name: foo # CHECK: body: | # CHECK-NEXT: bb.0.entry: # CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) -# CHECK-NEXT: liveins: %edi -# CHECK: CMP32ri8 %edi, 10, implicit-def %eflags -# CHECK-NEXT: JG_1 %bb.2, implicit killed %eflags +# CHECK-NEXT: liveins: $edi +# CHECK: CMP32ri8 $edi, 10, implicit-def $eflags +# CHECK-NEXT: JG_1 %bb.2, implicit killed $eflags # CHECK: bb.1.less: -# CHECK-NEXT: %eax = MOV32r0 implicit-def dead %eflags -# CHECK-NEXT: RETQ killed %eax +# CHECK-NEXT: $eax = MOV32r0 implicit-def dead $eflags +# CHECK-NEXT: RETQ killed $eax # CHECK: bb.2.exit: -# CHECK-NEXT: liveins: %edi -# CHECK: %eax = COPY killed %edi -# CHECK-NEXT: RETQ killed %eax +# CHECK-NEXT: liveins: $edi +# CHECK: $eax = COPY killed $edi +# CHECK-NEXT: RETQ killed $eax body: | bb.0.entry: successors: %bb.1, %bb.2 - liveins: %edi + liveins: $edi - CMP32ri8 %edi, 10, implicit-def %eflags + CMP32ri8 $edi, 10, implicit-def $eflags - JG_1 %bb.2, implicit killed %eflags + JG_1 %bb.2, implicit killed $eflags bb.1.less: - %eax = MOV32r0 implicit-def dead %eflags - RETQ killed %eax + $eax = MOV32r0 implicit-def dead $eflags + RETQ killed $eax bb.2.exit: - liveins: %edi - %eax = COPY killed %edi - RETQ killed %eax + liveins: $edi + $eax = COPY killed $edi + RETQ killed $eax ... --- name: bar tracksRegLiveness: true liveins: - - { reg: '%edi' } + - { reg: '$edi' } # CHECK-LABEL: name: bar # CHECK: body: | # CHECK-NEXT: bb.0.entry: # CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) -# CHECK-NEXT: liveins: %edi -# CHECK: CMP32ri8 %edi, 10, implicit-def %eflags -# CHECK-NEXT: JG_1 %bb.2, implicit killed %eflags +# CHECK-NEXT: liveins: $edi +# CHECK: CMP32ri8 $edi, 10, implicit-def $eflags +# CHECK-NEXT: JG_1 %bb.2, implicit killed $eflags # CHECK: bb.1.less: -# CHECK-NEXT: %eax = MOV32r0 implicit-def dead %eflags -# CHECK-NEXT: RETQ killed %eax +# CHECK-NEXT: $eax = MOV32r0 implicit-def dead $eflags +# CHECK-NEXT: RETQ killed $eax # CHECK: bb.2.exit: -# CHECK-NEXT: liveins: %edi -# CHECK: %eax = COPY killed %edi -# CHECK-NEXT: RETQ killed %eax +# CHECK-NEXT: liveins: $edi +# CHECK: $eax = COPY killed $edi +# CHECK-NEXT: RETQ killed $eax body: | bb.0.entry: successors: %bb.1, %bb.2 - liveins: %edi - CMP32ri8 %edi, 10, implicit-def %eflags - JG_1 %bb.2, implicit killed %eflags - bb.1.less: %eax = MOV32r0 implicit-def dead %eflags - RETQ killed %eax - - bb.2.exit: liveins: %edi - %eax = COPY killed %edi - RETQ killed %eax + liveins: $edi + CMP32ri8 $edi, 10, implicit-def $eflags + JG_1 %bb.2, implicit killed $eflags + bb.1.less: $eax = MOV32r0 implicit-def dead $eflags + RETQ killed $eax + + bb.2.exit: liveins: $edi + $eax = COPY killed $edi + RETQ killed $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/null-register-operands.mir b/llvm/test/CodeGen/MIR/X86/null-register-operands.mir index bb7a2e5688c..35b02cf3464 100644 --- a/llvm/test/CodeGen/MIR/X86/null-register-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/null-register-operands.mir @@ -15,8 +15,8 @@ name: deref body: | bb.0.entry: - ; CHECK: %eax = MOV32rm %rdi, 1, %noreg, 0, %noreg - ; CHECK-NEXT: RETQ %eax - %eax = MOV32rm %rdi, 1, _, 0, %noreg - RETQ %eax + ; CHECK: $eax = MOV32rm $rdi, 1, $noreg, 0, $noreg + ; CHECK-NEXT: RETQ $eax + $eax = MOV32rm $rdi, 1, _, 0, $noreg + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/register-mask-operands.mir b/llvm/test/CodeGen/MIR/X86/register-mask-operands.mir index c683a635f14..6d61a33e3d3 100644 --- a/llvm/test/CodeGen/MIR/X86/register-mask-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/register-mask-operands.mir @@ -22,18 +22,18 @@ name: compute body: | bb.0.body: - %eax = IMUL32rri8 %edi, 11, implicit-def %eflags - RETQ %eax + $eax = IMUL32rri8 $edi, 11, implicit-def $eflags + RETQ $eax ... --- # CHECK: name: foo name: foo body: | bb.0.entry: - ; CHECK: PUSH64r %rax - ; CHECK-NEXT: CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax - PUSH64r %rax, implicit-def %rsp, implicit %rsp - CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax - %rdx = POP64r implicit-def %rsp, implicit %rsp - RETQ %eax + ; CHECK: PUSH64r $rax + ; CHECK-NEXT: CALL64pcrel32 @compute, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax + PUSH64r $rax, implicit-def $rsp, implicit $rsp + CALL64pcrel32 @compute, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax + $rdx = POP64r implicit-def $rsp, implicit $rsp + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/register-operand-class-invalid0.mir b/llvm/test/CodeGen/MIR/X86/register-operand-class-invalid0.mir index 10a9f2d7ceb..c0eaddc6490 100644 --- a/llvm/test/CodeGen/MIR/X86/register-operand-class-invalid0.mir +++ b/llvm/test/CodeGen/MIR/X86/register-operand-class-invalid0.mir @@ -9,5 +9,5 @@ name: t body: | bb.0: ; CHECK: [[@LINE+1]]:10: register class specification expects a virtual register - %eax : gr32 = COPY %rdx + $eax : gr32 = COPY $rdx ... diff --git a/llvm/test/CodeGen/MIR/X86/register-operand-class-invalid1.mir b/llvm/test/CodeGen/MIR/X86/register-operand-class-invalid1.mir index 4be7fb38335..5d6777c63cc 100644 --- a/llvm/test/CodeGen/MIR/X86/register-operand-class-invalid1.mir +++ b/llvm/test/CodeGen/MIR/X86/register-operand-class-invalid1.mir @@ -8,7 +8,7 @@ name: t body: | bb.0: - %0 : gr32 = COPY %rdx + %0 : gr32 = COPY $rdx ; CHECK: [[@LINE+1]]:24: conflicting register classes, previously: GR32 NOOP implicit %0 : gr32_abcd ... diff --git a/llvm/test/CodeGen/MIR/X86/register-operand-class.mir b/llvm/test/CodeGen/MIR/X86/register-operand-class.mir index abdcda2a077..f62d7294eab 100644 --- a/llvm/test/CodeGen/MIR/X86/register-operand-class.mir +++ b/llvm/test/CodeGen/MIR/X86/register-operand-class.mir @@ -14,14 +14,14 @@ name: func body: | bb.0: - %0 : gr32 = COPY %rax - %1.sub_32bit : gr64 = COPY %eax - %rdx = COPY %1 - %2 = COPY %ecx - %ecx = COPY %2 : gr32 + %0 : gr32 = COPY $rax + %1.sub_32bit : gr64 = COPY $eax + $rdx = COPY %1 + %2 = COPY $ecx + $ecx = COPY %2 : gr32 - %3 : gr16 = COPY %bx - %bx = COPY %3 : gr16 + %3 : gr16 = COPY $bx + $bx = COPY %3 : gr16 - %4 : _(s32) = COPY %edx + %4 : _(s32) = COPY $edx ... diff --git a/llvm/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir b/llvm/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir index d4d3f5692e9..530a3bff97a 100644 --- a/llvm/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir +++ b/llvm/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir @@ -17,8 +17,8 @@ name: inc body: | bb.0.entry: ; CHECK: [[@LINE+1]]:42: register operands can't have target flags - %rax = MOV64rm target-flags(x86-got) %rip, 1, _, @G, _ - %eax = MOV32rm killed %rax, 1, _, 0, _ - %eax = INC32r killed %eax, implicit-def dead %eflags - RETQ %eax + $rax = MOV64rm target-flags(x86-got) $rip, 1, _, @G, _ + $eax = MOV32rm killed $rax, 1, _, 0, _ + $eax = INC32r killed $eax, implicit-def dead $eflags + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/renamable-register-flag.mir b/llvm/test/CodeGen/MIR/X86/renamable-register-flag.mir index 3854a2877c0..5b2f482449c 100644 --- a/llvm/test/CodeGen/MIR/X86/renamable-register-flag.mir +++ b/llvm/test/CodeGen/MIR/X86/renamable-register-flag.mir @@ -10,7 +10,7 @@ name: foo body: | ; CHECK: bb.0: bb.0: - ; CHECK: renamable %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags - renamable %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags - RETQ %eax + ; CHECK: renamable $eax = IMUL32rri8 $edi, 11, implicit-def dead $eflags + renamable $eax = IMUL32rri8 $edi, 11, implicit-def dead $eflags + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/roundtrip.mir b/llvm/test/CodeGen/MIR/X86/roundtrip.mir index 6d5c3516f33..94e562f5511 100644 --- a/llvm/test/CodeGen/MIR/X86/roundtrip.mir +++ b/llvm/test/CodeGen/MIR/X86/roundtrip.mir @@ -6,15 +6,15 @@ # CHECK: - { id: 1, class: gr32, preferred-register: '' } # CHECK: body: | # CHECK: bb.0: -# CHECK: %0:gr32 = MOV32r0 implicit-def %eflags +# CHECK: %0:gr32 = MOV32r0 implicit-def $eflags # CHECK: dead %1:gr32 = COPY %0 -# CHECK: MOV32mr undef %rcx, 1, %noreg, 0, %noreg, killed %0 :: (volatile store 4) -# CHECK: RETQ undef %eax +# CHECK: MOV32mr undef $rcx, 1, $noreg, 0, $noreg, killed %0 :: (volatile store 4) +# CHECK: RETQ undef $eax name: func0 body: | bb.0: - %0 : gr32 = MOV32r0 implicit-def %eflags + %0 : gr32 = MOV32r0 implicit-def $eflags dead %1 : gr32 = COPY %0 - MOV32mr undef %rcx, 1, _, 0, _, killed %0 :: (volatile store 4) - RETQ undef %eax + MOV32mr undef $rcx, 1, _, 0, _, killed %0 :: (volatile store 4) + RETQ undef $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir b/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir index 310fa6a1c53..5cae2a20c3a 100644 --- a/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir +++ b/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir @@ -16,19 +16,19 @@ name: test tracksRegLiveness: true # CHECK: registers: # CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '%esi' } -# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '%edi' } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '$esi' } +# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '$edi' } registers: - { id: 0, class: gr32 } - - { id: 1, class: gr32, preferred-register: '%esi' } - - { id: 2, class: gr32, preferred-register: '%edi' } + - { id: 1, class: gr32, preferred-register: '$esi' } + - { id: 2, class: gr32, preferred-register: '$edi' } body: | bb.0.body: - liveins: %edi, %esi + liveins: $edi, $esi - %1 = COPY %esi - %2 = COPY %edi - %2 = IMUL32rr %2, %1, implicit-def dead %eflags - %eax = COPY %2 - RETQ killed %eax + %1 = COPY $esi + %2 = COPY $edi + %2 = IMUL32rr %2, %1, implicit-def dead $eflags + $eax = COPY %2 + RETQ killed $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir b/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir index b292a023d52..0bad0772180 100644 --- a/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir +++ b/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir @@ -27,7 +27,7 @@ stack: - { id: 0, offset: -12, size: 4, alignment: 4 } body: | bb.0.entry: - MOV32mr %rsp, 1, _, -4, _, %edi - %eax = COPY %edi - RETQ %eax + MOV32mr $rsp, 1, _, -4, _, $edi + $eax = COPY $edi + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/stack-object-invalid-name.mir b/llvm/test/CodeGen/MIR/X86/stack-object-invalid-name.mir index 4572f106256..3a72dc4521e 100644 --- a/llvm/test/CodeGen/MIR/X86/stack-object-invalid-name.mir +++ b/llvm/test/CodeGen/MIR/X86/stack-object-invalid-name.mir @@ -22,7 +22,7 @@ stack: - { id: 0, name: x, offset: -12, size: 4, alignment: 4 } body: | bb.0.entry: - MOV32mr %rsp, 1, _, -4, _, %edi - %eax = MOV32rm %rsp, 1, _, -4, _ - RETQ %eax + MOV32mr $rsp, 1, _, -4, _, $edi + $eax = MOV32rm $rsp, 1, _, -4, _ + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir b/llvm/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir index 12f731e2f55..91b7951bf36 100644 --- a/llvm/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir +++ b/llvm/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir @@ -24,9 +24,9 @@ stack: - { id: 0, name: b, size: 4, alignment: 4 } body: | bb.0.entry: - %0 = COPY %edi + %0 = COPY $edi ; CHECK: [[@LINE+1]]:13: the name of the stack object '%stack.0' isn't 'x' MOV32mr %stack.0.x, 1, _, 0, _, %0 - %eax = COPY %0 - RETQ %eax + $eax = COPY %0 + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/stack-object-operands.mir b/llvm/test/CodeGen/MIR/X86/stack-object-operands.mir index 806caf6a290..76be7e074cd 100644 --- a/llvm/test/CodeGen/MIR/X86/stack-object-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/stack-object-operands.mir @@ -32,16 +32,16 @@ stack: body: | bb.0.entry: ; CHECK-LABEL: name: test - ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, %noreg, 0, %noreg - ; CHECK: MOV32mr %stack.0.b, 1, %noreg, 0, %noreg, [[MOV32rm]] - ; CHECK: MOV32mi %stack.1, 1, %noreg, 0, %noreg, 2 - ; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %stack.0.b, 1, %noreg, 0, %noreg - ; CHECK: %eax = COPY [[MOV32rm1]] - ; CHECK: RETL %eax + ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg + ; CHECK: MOV32mr %stack.0.b, 1, $noreg, 0, $noreg, [[MOV32rm]] + ; CHECK: MOV32mi %stack.1, 1, $noreg, 0, $noreg, 2 + ; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %stack.0.b, 1, $noreg, 0, $noreg + ; CHECK: $eax = COPY [[MOV32rm1]] + ; CHECK: RETL $eax %0 = MOV32rm %fixed-stack.0, 1, _, 0, _ MOV32mr %stack.0.b, 1, _, 0, _, %0 MOV32mi %stack.1, 1, _, 0, _, 2 %1 = MOV32rm %stack.0, 1, _, 0, _ - %eax = COPY %1 - RETL %eax + $eax = COPY %1 + RETL $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir b/llvm/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir index 0fccff0425e..f15f8368d26 100644 --- a/llvm/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir +++ b/llvm/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir @@ -19,7 +19,7 @@ name: test tracksRegLiveness: true liveins: - - { reg: '%edi' } + - { reg: '$edi' } frameInfo: maxAlignment: 8 stack: @@ -28,10 +28,10 @@ stack: - { id: 0, name: x, offset: -24, size: 8, alignment: 8 } body: | bb.0.entry: - liveins: %edi + liveins: $edi - MOV32mr %rsp, 1, _, -4, _, killed %edi - MOV64mi32 %rsp, 1, _, -16, _, 2 - %eax = MOV32rm %rsp, 1, _, -4, _ - RETQ %eax + MOV32mr $rsp, 1, _, -4, _, killed $edi + MOV64mi32 $rsp, 1, _, -16, _, 2 + $eax = MOV32rm $rsp, 1, _, -4, _ + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/stack-objects.mir b/llvm/test/CodeGen/MIR/X86/stack-objects.mir index a8492a82fe5..1e6e6882ef4 100644 --- a/llvm/test/CodeGen/MIR/X86/stack-objects.mir +++ b/llvm/test/CodeGen/MIR/X86/stack-objects.mir @@ -36,8 +36,8 @@ stack: - { id: 2, type: spill-slot, offset: -32, size: 4, alignment: 4 } body: | bb.0.entry: - MOV32mr %rsp, 1, _, -4, _, %edi - MOV64mi32 %rsp, 1, _, -16, _, 2 - %eax = MOV32rm %rsp, 1, _, -4, _ - RETQ %eax + MOV32mr $rsp, 1, _, -4, _, $edi + MOV64mi32 $rsp, 1, _, -16, _, 2 + $eax = MOV32rm $rsp, 1, _, -4, _ + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/standalone-register-error.mir b/llvm/test/CodeGen/MIR/X86/standalone-register-error.mir index c840dd52de1..009e514e770 100644 --- a/llvm/test/CodeGen/MIR/X86/standalone-register-error.mir +++ b/llvm/test/CodeGen/MIR/X86/standalone-register-error.mir @@ -12,12 +12,12 @@ registers: - { id: 0, class: gr32 } liveins: # CHECK: [[@LINE+1]]:13: unknown register name 'register' - - { reg: '%register', virtual-reg: '%0' } + - { reg: '$register', virtual-reg: '%0' } body: | bb.0.body: - liveins: %edi + liveins: $edi - %0 = COPY %edi - %eax = COPY %0 - RETQ %eax + %0 = COPY $edi + $eax = COPY %0 + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/subreg-on-physreg.mir b/llvm/test/CodeGen/MIR/X86/subreg-on-physreg.mir index 740d706433f..832576fbb68 100644 --- a/llvm/test/CodeGen/MIR/X86/subreg-on-physreg.mir +++ b/llvm/test/CodeGen/MIR/X86/subreg-on-physreg.mir @@ -8,5 +8,5 @@ name: t body: | bb.0: ; CHECK: [[@LINE+1]]:19: subregister index expects a virtual register - %eax.sub_8bit = COPY %bl + $eax.sub_8bit = COPY $bl ... diff --git a/llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir b/llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir index 4d8b24608b7..b1e96779c3f 100644 --- a/llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir @@ -19,16 +19,16 @@ registers: - { id: 1, class: gr8 } body: | bb.0.entry: - liveins: %edi, %eax + liveins: $edi, $eax ; CHECK-LABEL: name: t - ; CHECK: liveins: %edi, %eax - ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG %edi, %al, %subreg.sub_8bit - ; CHECK: [[EXTRACT_SUBREG:%[0-9]+]]:gr8 = EXTRACT_SUBREG %eax, %subreg.sub_8bit_hi - ; CHECK: %ax = REG_SEQUENCE [[EXTRACT_SUBREG]], %subreg.sub_8bit, [[EXTRACT_SUBREG]], %subreg.sub_8bit_hi - ; CHECK: RETQ %ax - %0 = INSERT_SUBREG %edi, %al, %subreg.sub_8bit - %1 = EXTRACT_SUBREG %eax, %subreg.sub_8bit_hi - %ax = REG_SEQUENCE %1, %subreg.sub_8bit, %1, %subreg.sub_8bit_hi - RETQ %ax + ; CHECK: liveins: $edi, $eax + ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG $edi, $al, %subreg.sub_8bit + ; CHECK: [[EXTRACT_SUBREG:%[0-9]+]]:gr8 = EXTRACT_SUBREG $eax, %subreg.sub_8bit_hi + ; CHECK: $ax = REG_SEQUENCE [[EXTRACT_SUBREG]], %subreg.sub_8bit, [[EXTRACT_SUBREG]], %subreg.sub_8bit_hi + ; CHECK: RETQ $ax + %0 = INSERT_SUBREG $edi, $al, %subreg.sub_8bit + %1 = EXTRACT_SUBREG $eax, %subreg.sub_8bit_hi + $ax = REG_SEQUENCE %1, %subreg.sub_8bit, %1, %subreg.sub_8bit_hi + RETQ $ax ... diff --git a/llvm/test/CodeGen/MIR/X86/subregister-operands.mir b/llvm/test/CodeGen/MIR/X86/subregister-operands.mir index caf342e2671..3361deb437c 100644 --- a/llvm/test/CodeGen/MIR/X86/subregister-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/subregister-operands.mir @@ -20,18 +20,18 @@ registers: - { id: 2, class: gr8 } body: | bb.0.entry: - liveins: %edi + liveins: $edi ; CHECK-LABEL: name: t - ; CHECK: liveins: %edi - ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi + ; CHECK: liveins: $edi + ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit - ; CHECK: [[AND8ri:%[0-9]+]]:gr8 = AND8ri [[COPY1]], 1, implicit-def %eflags - ; CHECK: %al = COPY [[AND8ri]] - ; CHECK: RETQ %al - %0 = COPY %edi + ; CHECK: [[AND8ri:%[0-9]+]]:gr8 = AND8ri [[COPY1]], 1, implicit-def $eflags + ; CHECK: $al = COPY [[AND8ri]] + ; CHECK: RETQ $al + %0 = COPY $edi %1 = COPY %0.sub_8bit - %2 = AND8ri %1, 1, implicit-def %eflags - %al = COPY %2 - RETQ %al + %2 = AND8ri %1, 1, implicit-def $eflags + $al = COPY %2 + RETQ $al ... diff --git a/llvm/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir b/llvm/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir index 5a22557f324..46e133b72ea 100644 --- a/llvm/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir +++ b/llvm/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir @@ -25,18 +25,18 @@ body: | ; CHECK-LABEL: bb.1.less: bb.0.entry: successors: %bb.1 (33), %bb.2(67) - liveins: %edi + liveins: $edi - CMP32ri8 %edi, 10, implicit-def %eflags - JG_1 %bb.2, implicit killed %eflags + CMP32ri8 $edi, 10, implicit-def $eflags + JG_1 %bb.2, implicit killed $eflags bb.1.less: - %eax = MOV32r0 implicit-def dead %eflags - RETQ killed %eax + $eax = MOV32r0 implicit-def dead $eflags + RETQ killed $eax bb.2.exit: - liveins: %edi + liveins: $edi - %eax = COPY killed %edi - RETQ killed %eax + $eax = COPY killed $edi + RETQ killed $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/successor-basic-blocks.mir b/llvm/test/CodeGen/MIR/X86/successor-basic-blocks.mir index ffeb04af9e4..d8b9f5e5825 100644 --- a/llvm/test/CodeGen/MIR/X86/successor-basic-blocks.mir +++ b/llvm/test/CodeGen/MIR/X86/successor-basic-blocks.mir @@ -35,20 +35,20 @@ body: | ; CHECK-LABEL: bb.1.less: bb.0.entry: successors: %bb.1.less, %bb.2.exit - liveins: %edi + liveins: $edi - CMP32ri8 %edi, 10, implicit-def %eflags - JG_1 %bb.2.exit, implicit killed %eflags + CMP32ri8 $edi, 10, implicit-def $eflags + JG_1 %bb.2.exit, implicit killed $eflags bb.1.less: - %eax = MOV32r0 implicit-def dead %eflags - RETQ killed %eax + $eax = MOV32r0 implicit-def dead $eflags + RETQ killed $eax bb.2.exit: - liveins: %edi + liveins: $edi - %eax = COPY killed %edi - RETQ killed %eax + $eax = COPY killed $edi + RETQ killed $eax ... --- name: bar @@ -59,24 +59,24 @@ body: | ; CHECK-LABEL: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000), %bb.2(0x00000000) bb.0.entry: - liveins: %edi + liveins: $edi successors: %bb.1 successors: %bb.2 - CMP32ri8 %edi, 10, implicit-def %eflags - JG_1 %bb.2, implicit killed %eflags + CMP32ri8 $edi, 10, implicit-def $eflags + JG_1 %bb.2, implicit killed $eflags ; Verify that we can have an empty list of successors. ; CHECK-LABEL: bb.1: - ; CHECK-NEXT: %eax = MOV32r0 implicit-def dead %eflags + ; CHECK-NEXT: $eax = MOV32r0 implicit-def dead $eflags bb.1: successors: - %eax = MOV32r0 implicit-def dead %eflags - RETQ killed %eax + $eax = MOV32r0 implicit-def dead $eflags + RETQ killed $eax bb.2: - liveins: %edi + liveins: $edi - %eax = COPY killed %edi - RETQ killed %eax + $eax = COPY killed $edi + RETQ killed $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir b/llvm/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir index f4ea327edea..412db1dfd22 100644 --- a/llvm/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir +++ b/llvm/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir @@ -12,13 +12,13 @@ name: test tracksRegLiveness: true liveins: - - { reg: '%rdi' } + - { reg: '$rdi' } body: | bb.0.entry: - liveins: %rdi + liveins: $rdi ; CHECK: [[@LINE+1]]:58: use of invalid tied-def operand index '0'; the operand #0 isn't a defined register - INLINEASM &"$foo", 1, 2818058, def %rdi, 2147483657, killed %rdi(tied-def 0) - %rax = COPY killed %rdi - RETQ killed %rax + INLINEASM &"$foo", 1, 2818058, def $rdi, 2147483657, killed $rdi(tied-def 0) + $rax = COPY killed $rdi + RETQ killed $rax ... diff --git a/llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir b/llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir index 1ddf649f76a..8f531d96d1d 100644 --- a/llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir +++ b/llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir @@ -14,9 +14,9 @@ name: foo body: | bb.0.entry: - liveins: %rdi + liveins: $rdi ; CHECK: Tied physical registers must match. - %rbx = AND64rm killed %rdx, killed %rdi, 1, _, 0, _, implicit-def dead %eflags - RETQ %rbx + $rbx = AND64rm killed $rdx, killed $rdi, 1, _, 0, _, implicit-def dead $eflags + RETQ $rbx ... diff --git a/llvm/test/CodeGen/MIR/X86/undef-register-flag.mir b/llvm/test/CodeGen/MIR/X86/undef-register-flag.mir index 2c332d848bb..4fe938f079c 100644 --- a/llvm/test/CodeGen/MIR/X86/undef-register-flag.mir +++ b/llvm/test/CodeGen/MIR/X86/undef-register-flag.mir @@ -23,16 +23,16 @@ name: compute body: | bb.0.body: - %eax = IMUL32rri8 %edi, 11, implicit-def %eflags - RETQ %eax + $eax = IMUL32rri8 $edi, 11, implicit-def $eflags + RETQ $eax ... --- name: foo body: | bb.0.entry: - ; CHECK: PUSH64r undef %rax - PUSH64r undef %rax, implicit-def %rsp, implicit %rsp - CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax - %rdx = POP64r implicit-def %rsp, implicit %rsp - RETQ %eax + ; CHECK: PUSH64r undef $rax + PUSH64r undef $rax, implicit-def $rsp, implicit $rsp + CALL64pcrel32 @compute, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax + $rdx = POP64r implicit-def $rsp, implicit $rsp + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir b/llvm/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir index 35879b7036d..7462290472a 100644 --- a/llvm/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir +++ b/llvm/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir @@ -32,6 +32,6 @@ body: | MOV32mr %stack.0, 1, _, 0, _, %0 MOV32mi %stack.1, 1, _, 0, _, 2 %1 = MOV32rm %stack.0, 1, _, 0, _ - %eax = COPY %1 - RETL %eax + $eax = COPY %1 + RETL $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/undefined-global-value.mir b/llvm/test/CodeGen/MIR/X86/undefined-global-value.mir index e717c1ee597..881e114b25a 100644 --- a/llvm/test/CodeGen/MIR/X86/undefined-global-value.mir +++ b/llvm/test/CodeGen/MIR/X86/undefined-global-value.mir @@ -19,8 +19,8 @@ name: inc body: | bb.0.entry: ; CHECK: [[@LINE+1]]:32: use of undefined global value '@2' - %rax = MOV64rm %rip, 1, _, @2, _ - %eax = MOV32rm %rax, 1, _, 0, _ - %eax = INC32r %eax - RETQ %eax + $rax = MOV64rm $rip, 1, _, @2, _ + $eax = MOV32rm $rax, 1, _, 0, _ + $eax = INC32r $eax + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir b/llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir index 5c2a45eec2a..e5fde201fb9 100644 --- a/llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir +++ b/llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir @@ -21,9 +21,9 @@ body: | bb.0.entry: successors: %bb.1.block ; CHECK: [[@LINE+1]]:51: use of undefined IR block '%ir-block."block "' - %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block."block "), _ - MOV64mr %rip, 1, _, @addr, _, killed %rax - JMP64m %rip, 1, _, @addr, _ + $rax = LEA64r $rip, 1, _, blockaddress(@test, %ir-block."block "), _ + MOV64mr $rip, 1, _, @addr, _, killed $rax + JMP64m $rip, 1, _, @addr, _ bb.1.block (address-taken): RETQ diff --git a/llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir b/llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir index ef7dd4802ac..be0690b02a4 100644 --- a/llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir +++ b/llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir @@ -20,9 +20,9 @@ body: | bb.0.entry: successors: %bb.1 ; CHECK: [[@LINE+1]]:51: use of undefined IR block '%ir-block.1' - %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.1), _ - MOV64mr %rip, 1, _, @addr, _, killed %rax - JMP64m %rip, 1, _, @addr, _ + $rax = LEA64r $rip, 1, _, blockaddress(@test, %ir-block.1), _ + MOV64mr $rip, 1, _, @addr, _, killed $rax + JMP64m $rip, 1, _, @addr, _ bb.1 (address-taken): RETQ diff --git a/llvm/test/CodeGen/MIR/X86/undefined-jump-table-id.mir b/llvm/test/CodeGen/MIR/X86/undefined-jump-table-id.mir index 765bb9d97d1..f6543e6c742 100644 --- a/llvm/test/CodeGen/MIR/X86/undefined-jump-table-id.mir +++ b/llvm/test/CodeGen/MIR/X86/undefined-jump-table-id.mir @@ -39,35 +39,35 @@ body: | bb.0.entry: successors: %bb.2.def, %bb.1.entry - %eax = MOV32rr %edi, implicit-def %rax - CMP32ri8 %edi, 3, implicit-def %eflags - JA_1 %bb.2.def, implicit %eflags + $eax = MOV32rr $edi, implicit-def $rax + CMP32ri8 $edi, 3, implicit-def $eflags + JA_1 %bb.2.def, implicit $eflags bb.1.entry: successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4 ; CHECK: [[@LINE+1]]:31: use of undefined jump table '%jump-table.2' - %rcx = LEA64r %rip, 1, _, %jump-table.2, _ - %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _ - %rax = ADD64rr %rax, %rcx, implicit-def %eflags - JMP64r %rax + $rcx = LEA64r $rip, 1, _, %jump-table.2, _ + $rax = MOVSX64rm32 $rcx, 4, $rax, 0, _ + $rax = ADD64rr $rax, $rcx, implicit-def $eflags + JMP64r $rax bb.2.def: - %eax = MOV32r0 implicit-def %eflags - RETQ %eax + $eax = MOV32r0 implicit-def $eflags + RETQ $eax bb.3.lbl1: - %eax = MOV32ri 1 - RETQ %eax + $eax = MOV32ri 1 + RETQ $eax bb.4.lbl2: - %eax = MOV32ri 2 - RETQ %eax + $eax = MOV32ri 2 + RETQ $eax bb.5.lbl3: - %eax = MOV32ri 4 - RETQ %eax + $eax = MOV32ri 4 + RETQ $eax bb.6.lbl4: - %eax = MOV32ri 8 - RETQ %eax + $eax = MOV32ri 8 + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/undefined-named-global-value.mir b/llvm/test/CodeGen/MIR/X86/undefined-named-global-value.mir index 435257b8fac..43c8d141432 100644 --- a/llvm/test/CodeGen/MIR/X86/undefined-named-global-value.mir +++ b/llvm/test/CodeGen/MIR/X86/undefined-named-global-value.mir @@ -19,8 +19,8 @@ name: inc body: | bb.0.entry: ; CHECK: [[@LINE+1]]:32: use of undefined global value '@GG' - %rax = MOV64rm %rip, 1, _, @GG, _ - %eax = MOV32rm %rax, 1, _, 0, _ - %eax = INC32r %eax - RETQ %eax + $rax = MOV64rm $rip, 1, _, @GG, _ + $eax = MOV32rm $rax, 1, _, 0, _ + $eax = INC32r $eax + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/undefined-stack-object.mir b/llvm/test/CodeGen/MIR/X86/undefined-stack-object.mir index cbf0322860e..aeb6b2abfe8 100644 --- a/llvm/test/CodeGen/MIR/X86/undefined-stack-object.mir +++ b/llvm/test/CodeGen/MIR/X86/undefined-stack-object.mir @@ -21,9 +21,9 @@ stack: - { id: 0, name: b, size: 4, alignment: 4 } body: | bb.0.entry: - %0 = COPY %edi + %0 = COPY $edi ; CHECK: [[@LINE+1]]:13: use of undefined stack object '%stack.2' MOV32mr %stack.2, 1, _, 0, _, %0 - %eax = COPY %0 - RETQ %eax + $eax = COPY %0 + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir b/llvm/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir index 42e94c1ce5a..4ad8519d268 100644 --- a/llvm/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir +++ b/llvm/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir @@ -13,12 +13,12 @@ name: test tracksRegLiveness: true liveins: - - { reg: '%rdi' } + - { reg: '$rdi' } body: | bb.0.entry: - liveins: %rdi + liveins: $rdi ; CHECK: [[@LINE+1]]:60: use of undefined IR value '%ir.c' - %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.c) - RETQ %eax + $eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load 4 from %ir.c) + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/undefined-virtual-register.mir b/llvm/test/CodeGen/MIR/X86/undefined-virtual-register.mir index 8a6222481d6..665e37fc15c 100644 --- a/llvm/test/CodeGen/MIR/X86/undefined-virtual-register.mir +++ b/llvm/test/CodeGen/MIR/X86/undefined-virtual-register.mir @@ -17,9 +17,9 @@ registers: - { id: 0, class: gr32 } body: | bb.0.entry: - %0 = COPY %edi + %0 = COPY $edi ; CHECK: Cannot determine class/bank of virtual register 1 in function 'test' - %eax = COPY %1 - RETQ %eax + $eax = COPY %1 + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/unexpected-type-phys.mir b/llvm/test/CodeGen/MIR/X86/unexpected-type-phys.mir index df0f849bc18..953b9f666bf 100644 --- a/llvm/test/CodeGen/MIR/X86/unexpected-type-phys.mir +++ b/llvm/test/CodeGen/MIR/X86/unexpected-type-phys.mir @@ -7,7 +7,7 @@ name: test_size_physreg registers: body: | bb.0.entry: - liveins: %edi + liveins: $edi ; CHECK: [[@LINE+1]]:10: unexpected type on physical register - %edi(s32) = G_ADD i32 %edi, %edi + $edi(s32) = G_ADD i32 $edi, $edi ... diff --git a/llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir b/llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir index 0634fb2e0ed..c18a11c5153 100644 --- a/llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir +++ b/llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir @@ -23,14 +23,14 @@ name: foo body: | bb.0.entry: - %eax = MOV32rm %rdi, 1, _, 0, _ - CMP32ri8 %eax, 10, implicit-def %eflags + $eax = MOV32rm $rdi, 1, _, 0, _ + CMP32ri8 $eax, 10, implicit-def $eflags ; CHECK: [[@LINE+1]]:10: use of undefined machine basic block #4 - JG_1 %bb.4, implicit %eflags + JG_1 %bb.4, implicit $eflags bb.1: - %eax = MOV32r0 implicit-def %eflags + $eax = MOV32r0 implicit-def $eflags bb.2: - RETQ %eax + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir b/llvm/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir index ddd5686b0cf..9c17655dd8b 100644 --- a/llvm/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir +++ b/llvm/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir @@ -13,13 +13,13 @@ name: inc tracksRegLiveness: true liveins: - - { reg: '%rdi' } + - { reg: '$rdi' } body: | bb.0.entry: - liveins: %rdi + liveins: $rdi ; CHECK: [[@LINE+1]]:60: use of unknown metadata keyword '!tba' - %eax = MOV32rm %rdi, 1, _, 0, _ :: (load 4 from %ir.x, !tba !0) - %eax = INC32r killed %eax, implicit-def dead %eflags - MOV32mr killed %rdi, 1, _, 0, _, %eax :: (store 4 into %ir.x) - RETQ %eax + $eax = MOV32rm $rdi, 1, _, 0, _ :: (load 4 from %ir.x, !tba !0) + $eax = INC32r killed $eax, implicit-def dead $eflags + MOV32mr killed $rdi, 1, _, 0, _, $eax :: (store 4 into %ir.x) + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/unknown-metadata-node.mir b/llvm/test/CodeGen/MIR/X86/unknown-metadata-node.mir index 3c709eb9423..d4cca2ae14c 100644 --- a/llvm/test/CodeGen/MIR/X86/unknown-metadata-node.mir +++ b/llvm/test/CodeGen/MIR/X86/unknown-metadata-node.mir @@ -48,10 +48,10 @@ stack: - { id: 0, name: x.addr, size: 4, alignment: 4 } body: | bb.0.entry: - %0 = COPY %edi + %0 = COPY $edi ; CHECK: [[@LINE+1]]:21: use of undefined metadata '!42' DBG_VALUE _, 0, !42, !13 MOV32mr %stack.0.x.addr, 1, _, 0, _, %0 - %eax = COPY %0 - RETQ %eax + $eax = COPY %0 + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir b/llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir index 5ba6402353e..de4942b53e9 100644 --- a/llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir +++ b/llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir @@ -22,14 +22,14 @@ name: foo body: | bb.0.entry: - %eax = MOV32rm %rdi, 1, _, 0, _ - CMP32ri8 %eax, 10, implicit-def %eflags + $eax = MOV32rm $rdi, 1, _, 0, _ + CMP32ri8 $eax, 10, implicit-def $eflags ; CHECK: [[@LINE+1]]:10: the name of machine basic block #2 isn't 'hit' - JG_1 %bb.2.hit, implicit %eflags + JG_1 %bb.2.hit, implicit $eflags bb.1.less: - %eax = MOV32r0 implicit-def %eflags + $eax = MOV32r0 implicit-def $eflags bb.2.exit: - RETQ %eax + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/unknown-register.mir b/llvm/test/CodeGen/MIR/X86/unknown-register.mir index 74e9bfa7215..37c30f6cb31 100644 --- a/llvm/test/CodeGen/MIR/X86/unknown-register.mir +++ b/llvm/test/CodeGen/MIR/X86/unknown-register.mir @@ -15,6 +15,6 @@ name: foo body: | bb.0.entry: ; CHECK: [[@LINE+1]]:5: unknown register name 'xax' - %xax = MOV32r0 - RETQ %xax + $xax = MOV32r0 + RETQ $xax ... diff --git a/llvm/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir b/llvm/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir index 1f4f9c63157..18eb3e73566 100644 --- a/llvm/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir +++ b/llvm/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir @@ -20,6 +20,6 @@ registers: body: | bb.0.entry: ; CHECK: [[@LINE+1]]:35: unknown subregister index 'bit8' - %0 = INSERT_SUBREG %edi, %al, %subreg.bit8 + %0 = INSERT_SUBREG $edi, $al, %subreg.bit8 RETQ %0 ... diff --git a/llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir b/llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir index 090ca52930a..d5cbb06aac5 100644 --- a/llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir +++ b/llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir @@ -19,10 +19,10 @@ registers: - { id: 2, class: gr8 } body: | bb.0.entry: - %0 = COPY %edi + %0 = COPY $edi ; CHECK: [[@LINE+1]]:18: use of unknown subregister index 'bit8' %1 = COPY %0.bit8 - %2 = AND8ri %1, 1, implicit-def %eflags - %al = COPY %2 - RETQ %al + %2 = AND8ri %1, 1, implicit-def $eflags + $al = COPY %2 + RETQ $al ... diff --git a/llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir b/llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir index e3c331a780a..5fd5435860d 100644 --- a/llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir +++ b/llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir @@ -37,8 +37,8 @@ stack: - { id: 2, name: y, type: variable-sized, offset: -32, alignment: 1 } body: | bb.0.entry: - MOV32mr %rsp, 1, _, -4, _, %edi - MOV64mi32 %rsp, 1, _, -16, _, 2 - %eax = MOV32rm %rsp, 1, _, -4, _ - RETQ %eax + MOV32mr $rsp, 1, _, -4, _, $edi + MOV64mi32 $rsp, 1, _, -16, _, 2 + $eax = MOV32rm $rsp, 1, _, -4, _ + RETQ $eax ... diff --git a/llvm/test/CodeGen/MIR/X86/virtual-registers.mir b/llvm/test/CodeGen/MIR/X86/virtual-registers.mir index 6e298910dcb..d3d25692a6f 100644 --- a/llvm/test/CodeGen/MIR/X86/virtual-registers.mir +++ b/llvm/test/CodeGen/MIR/X86/virtual-registers.mir @@ -43,24 +43,24 @@ registers: body: | bb.0.entry: successors: %bb.2.exit, %bb.1.less - liveins: %edi - ; CHECK: %0:gr32 = COPY %edi + liveins: $edi + ; CHECK: %0:gr32 = COPY $edi ; CHECK-NEXT: %1:gr32 = SUB32ri8 %0, 10 - %0 = COPY %edi - %1 = SUB32ri8 %0, 10, implicit-def %eflags - JG_1 %bb.2.exit, implicit %eflags + %0 = COPY $edi + %1 = SUB32ri8 %0, 10, implicit-def $eflags + JG_1 %bb.2.exit, implicit $eflags JMP_1 %bb.1.less bb.1.less: ; CHECK: %2:gr32 = MOV32r0 - ; CHECK-NEXT: %eax = COPY %2 - %2 = MOV32r0 implicit-def %eflags - %eax = COPY %2 - RETQ %eax + ; CHECK-NEXT: $eax = COPY %2 + %2 = MOV32r0 implicit-def $eflags + $eax = COPY %2 + RETQ $eax bb.2.exit: - %eax = COPY %0 - RETQ %eax + $eax = COPY %0 + RETQ $eax ... --- name: foo @@ -77,23 +77,23 @@ registers: body: | bb.0.entry: successors: %bb.2.exit, %bb.1.less - liveins: %edi - ; CHECK: %0:gr32 = COPY %edi + liveins: $edi + ; CHECK: %0:gr32 = COPY $edi ; CHECK-NEXT: %1:gr32 = SUB32ri8 %0, 10 - %2 = COPY %edi - %0 = SUB32ri8 %2, 10, implicit-def %eflags - JG_1 %bb.2.exit, implicit %eflags + %2 = COPY $edi + %0 = SUB32ri8 %2, 10, implicit-def $eflags + JG_1 %bb.2.exit, implicit $eflags JMP_1 %bb.1.less bb.1.less: ; CHECK: %2:gr32 = MOV32r0 - ; CHECK-NEXT: %eax = COPY %2 - %10 = MOV32r0 implicit-def %eflags - %eax = COPY %10 - RETQ %eax + ; CHECK-NEXT: $eax = COPY %2 + %10 = MOV32r0 implicit-def $eflags + $eax = COPY %10 + RETQ $eax bb.2.exit: - ; CHECK: %eax = COPY %0 - %eax = COPY %2 - RETQ %eax + ; CHECK: $eax = COPY %0 + $eax = COPY %2 + RETQ $eax ... |
