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* [ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio2020-01-141-1/+1
* [llvm][MIRVRegNamerUtils] Adding hashing on FrameIndex MachineOperands.Puyan Lotfi2020-01-131-0/+23
* Reverting, broke some bots. Need further investigation.Diogo Sampaio2020-01-101-1/+1
* [ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio2020-01-101-1/+1
* llc: Change behavior of -mcpu with existing attributeMatt Arsenault2020-01-071-2/+5
* llc/MIR: Fix setFunctionAttributes for MIR functionsMatt Arsenault2020-01-062-0/+78
* [ARM][THUMB2] Allow emitting T3 types of add and subDiogo Sampaio2019-12-301-0/+88
* Migrate function attribute "no-frame-pointer-elim"="false" to "frame-pointer"...Fangrui Song2019-12-2416-16/+16
* Migrate function attribute "no-frame-pointer-elim" to "frame-pointer"="all" a...Fangrui Song2019-12-241-1/+1
* [llvm][MIRVRegNamerUtils] Adding hashing on CImm / FPImm MachineOperands.Puyan Lotfi2019-12-161-0/+14
* [llvm][MIRVRegNamerUtils] Adding hashing on memoperands.Puyan Lotfi2019-12-111-0/+42
* [llvm][MIRVRegNamerUtil] Adding hashing against MachineInstr flags.Puyan Lotfi2019-12-101-0/+37
* [llvm] Fixing MIRVRegNamerUtils to properly handle 2+ MachineBasicBlocks.Puyan Lotfi2019-12-041-0/+61
* [MIRNamer]: Make the check lines in the test robust with regex.Aditya Nandakumar2019-11-164-42/+41
* [MirNamer][Canonicalizer]: Perform instruction semantic based renamingAditya Nandakumar2019-11-154-40/+48
* [MIR] Add MIR parsing for heap alloc site instruction markersAmy Huang2019-11-051-0/+42
* AMDGPU: Add default denormal mode to MachineFunctionInfoMatt Arsenault2019-11-012-0/+27
* [X86] Model MXCSR for all SSE instructionsCraig Topper2019-10-303-44/+44
* [BranchFolding] skip debug instr to avoid code changeJeremy Morse2019-10-291-0/+109
* [MIParser] Set RegClassOrRegBank during instruction parsingPetar Avramovic2019-10-221-9/+7
* [MIPS GlobalISel] Select MSA vector generic and builtin addPetar Avramovic2019-10-222-0/+68
* [Alignment] Migrate Attribute::getWith(Stack)AlignmentGuillaume Chatelet2019-10-152-6/+9
* Print quoted backslashes in LLVM IR as \\ instead of \5CReid Kleckner2019-10-101-1/+1
* [WebAssembly] Fix tests missed in rL374235Thomas Lively2019-10-092-2/+2
* [WebAssembly] Make returns variadicThomas Lively2019-10-091-1/+1
* [AMDGPU] Extend buffer intrinsics with swizzlingPiotr Sobczak2019-10-026-22/+22
* Add a missing space in a MIR parser error messageDavid Stenberg2019-09-201-1/+1
* [PowerPC][NFC] Move codegen tests to PowerPC from MIR/PowerPCJinsong Ji2019-09-134-444/+0
* [PowerPC][MCP][NFC] Pre-commit test cases for https://reviews.llvm.org/D65267Kai Luo2019-09-121-0/+281
* [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir...Guillaume Chatelet2019-09-1113-21/+21
* [MIR] Change test case to read from stdin instead of fileMikael Holmen2019-09-061-1/+1
* [MIR] MIRNamer pass for improving MIR test authoring experience.Puyan Lotfi2019-09-051-0/+90
* [mir-canon][NFC] Adding -verify-machineinstrs to mir-canon tests.Puyan Lotfi2019-09-052-9/+10
* AMDGPU: Add amdgpu-32bit-address-high-bits to MIR serializationMatt Arsenault2019-08-272-1/+16
* [DebugInfo] Allow bundled calls in the MIR's call site infoDavid Stenberg2019-08-191-0/+47
* [DebugInfo] MCP: collect and update DBG_VALUEs encountered in local blockJeremy Morse2019-08-141-0/+7
* GlobalISel: Add more verifier checks for G_SHUFFLE_VECTORMatt Arsenault2019-08-131-9/+9
* GlobalISel: Change representation of shuffle masksMatt Arsenault2019-08-135-0/+248
* [PowerPC][Peephole] Check if `extsw`'s second operand is a virtual registerKai Luo2019-08-021-2/+3
* AMDGPU/LoadStoreOptimizer: combine MMOs when merging instructionsTom Stellard2019-07-291-2/+2
* [PowerPC][NFC] Precommit a test case where ppc-mi-peepholes miscompiles extswsliKai Luo2019-07-221-0/+66
* AMDGPU: Serialize mode from MachineFunctionInfoMatt Arsenault2019-07-102-0/+69
* AMDGPU: Make s34 the FP registerMatt Arsenault2019-07-081-2/+2
* [AMDGPU] Enable serializing of argument info.Michael Liao2019-07-032-0/+80
* [MachineFunction] Base support for call site info trackingDjordje Todorovic2019-06-274-0/+92
* AMDGPU: Write LDS objects out as global symbols in code generationNicolai Haehnle2019-06-251-1/+1
* AMDGPU: Always use s33 for global scratch wave offsetMatt Arsenault2019-06-201-2/+2
* Rename ExpandISelPseudo->FinalizeISel, delay register reservationMatt Arsenault2019-06-193-8/+8
* [X86] Introduce new MOVSSrm/MOVSDrm opcodes that use VR128 register class.Craig Topper2019-06-181-3/+3
* [lit] Delete empty lines at the end of lit.local.cfg NFCFangrui Song2019-06-171-1/+0
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