vhdl2vl - vhdl2vl

	Commit message (Collapse)	Author	Age	Files	Lines
*	Allow second argument to CONVFUNC_2 to be expr	Larry Doolittle	2017-11-22	1	-1/+1
\| \| \| \| \|	Adds one more shift/reduce conflict. Include test case.
*	Experimental support of exponentiation	Rodrigo Alejandro Melo	2017-11-21	1	-0/+4
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*	Removed extra parentheses when parentheses are used	Rodrigo Alejandro Melo	2017-11-17	1	-1/+1
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*	Removed unuseful parentheses	Rodrigo Alejandro Melo	2017-11-17	1	-2/+2
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*	Modified to use ',' to separate sensitivity list in verilog 2001	Rodrigo Alejandro Melo	2017-02-17	1	-1/+1
\| \| \| \|	Changes applied to translated_examples.
*	Changed translated_examples due that Verilog 2001 is now the default	Rodrigo Alejandro Melo	2017-02-17	1	-7/+3
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*	Added command line option --quiet	Rodrigo Alejandro Melo	2017-02-17	1	-21/+0
\| \| \| \| \|	Used to avoid header on the generated verilog file. Is a problem for regression tests. Header was removed from translated_examples.
*	Added analysis of examples with GHDL	Rodrigo Alejandro Melo	2017-02-14	1	-3/+3
\| \| \| \| \| \| \| \|	Some examples were corrected according GHDL complains. Corresponding traslated_examples were modified. Use of synopsys libraries was removed. Translation of gh_fifo_async16_sr.vhd fails (complains about 'unsigned'). The problem was comented.
*	Space deleted in the <size>'<radix><number> notation	Rodrigo Alejandro Melo	2017-02-09	1	-1/+1
\| \| \| \| \| \| \|	It seems to be the more common approach and the VHDL notation BASE#NUMBER# is translated without spaces. On the other hand, the space gives an error with Yosys synthesizer. Files on translated_examples were modified.
*	vhd2vl-2.5	Larry Doolittle	2015-09-20	1	-2/+2
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*	vhd2vl-2.4	Larry Doolittle	2015-09-20	1	-1/+4
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*	vhd2vl-2.3	Larry Doolittle	2015-09-20	1	-2/+2
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*	vhd2vl-2.2	Larry Doolittle	2015-09-20	1	-0/+56