Changed translated_examples due that Verilog 2001 is now the default

1 files changed, 3 insertions, 7 deletions

diff --git a/translated_examples/expr.v b/translated_examples/expr.v
index 09c08e1..120fba3 100644
--- a/translated_examples/expr.v
+++ b/translated_examples/expr.v
@@ -1,16 +1,12 @@
 // no timescale needed
 
 module expr(
-reset,
-sysclk,
-ival
+input wire reset,
+input wire sysclk,
+input wire ival
 );
 
-input reset, sysclk, ival;
 
-wire reset;
-wire sysclk;
-wire ival;
 
 
 reg [13:0] foo;