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With test case!
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Makes sign extension idiom work in my code base
Test case added, doesn't break any others
Please test on your code!
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'test' was repeated as entity/module name
'config' was used as port name and is a reserved word in Verilog.
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Because the resulting verilog had the unsupported notation BASE#NUMBER#.
Moreover, the 'ERROR:' string was added when an error is informed.
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Some examples were corrected according GHDL complains.
Corresponding traslated_examples were modified.
Use of synopsys libraries was removed.
Translation of gh_fifo_async16_sr.vhd fails (complains about 'unsigned').
The problem was comented.
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Also support was added for real numbers especially thinking in generics.
Files called scientific.vhd and scientific.v were added for test.
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