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| author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2017-11-28 20:28:24 -0800 |
|---|---|---|
| committer | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2017-11-28 20:28:24 -0800 |
| commit | 051a68e5336ee1f575518be08e5c3e6b2b549c42 (patch) | |
| tree | e714fee06958a23d313d8168eaeb1153835827a4 /examples/based.vhd | |
| parent | 28e612f9b63fce6ea7fe933ddfcd39e7f132cd4c (diff) | |
| download | vhdl2vl-051a68e5336ee1f575518be08e5c3e6b2b549c42.tar.gz vhdl2vl-051a68e5336ee1f575518be08e5c3e6b2b549c42.zip | |
Add testcase for underscore in NATURAL
Diffstat (limited to 'examples/based.vhd')
| -rw-r--r-- | examples/based.vhd | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/examples/based.vhd b/examples/based.vhd index 1a8d2a1..7020b83 100644 --- a/examples/based.vhd +++ b/examples/based.vhd @@ -4,9 +4,10 @@ USE IEEE.std_logic_1164.all; entity based is port( sysclk : in std_logic); end based; architecture rtl of based is - signal foo,foo2,foo8,foo10,foo11,foo16 : integer; + signal foo,foo1,foo2,foo8,foo10,foo11,foo16 : integer; begin foo <= 123; + foo1 <= 123_456; foo2 <= 2#00101101110111#; foo8 <= 8#0177362#; foo10<= 10#01234#; |
