Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Bump FPGA version numberHEADv1.08master | Raptor Engineering Development Team | 2019-07-24 | 1 | -1/+1 |
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* | Fix poweroff fail for Talos lite | Xing Zhao | 2019-07-24 | 1 | -6/+6 |
| | | | | | | | | Talos lite has only one socket and unmounted all the components related to the second CPU. False power good of the second CPU's power may casue the system poweroff fail. So gate the power good of the second CPU's power by the present signal of the second CPU. Signed-off-by: Xing Zhao <zxingsh@cn.ibm.com> | ||||
* | Bump FPGA version number | Raptor Engineering Development Team | 2019-05-15 | 1 | -1/+1 |
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* | Use onboard oscillator on PCB revision 1.01 and higher | Raptor Engineering Development Team | 2019-04-30 | 2 | -40/+21 |
| | | | | This breaks compatibility with PCB revision 1.00 | ||||
* | Add missing build dependency to READMEtalos-pcb-rev1.00 | Raptor Engineering Development Team | 2019-04-29 | 1 | -1/+1 |
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* | Add initial README.md file | Raptor Engineering Development Team | 2019-04-29 | 1 | -0/+27 |
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* | Add initial pre-PAR simulation framework from internal files | Raptor Engineering Development Team | 2019-03-14 | 3 | -9/+150 |
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* | Fix regulator test modev1.07 | Raptor Engineering Development Team | 2018-06-14 | 1 | -6/+8 |
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* | Add regulator test mode for manufacturing | Raptor Engineering Development Team | 2018-06-11 | 1 | -7/+9 |
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* | Enable pullup on secondary CPU presence detect pin | Raptor Engineering Development Team | 2018-06-06 | 2 | -3/+13 |
| | | | | Bump FPGA version | ||||
* | Fix LICENSE textv1.06.1 | Raptor Engineering Development Team | 2018-05-17 | 1 | -1/+1 |
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* | Remove ATX power good filtering logicv1.06 | Raptor Engineering Development Team | 2018-05-13 | 1 | -23/+1 |
| | | | | | ATX PG must remain high for minimum periods according to the specification Don't try to work around faulty external power supply designs | ||||
* | Move ATX force enable to I2C register 0x33 | Raptor Engineering Development Team | 2018-05-13 | 2 | -13/+22 |
| | | | | | | Expose mode select jumper to host Switch ATX PG filter to slower clock source and reduce counter width Bump FPGA version in preparation for release | ||||
* | Extend ATX power enable signal | Raptor Engineering Development Team | 2018-05-02 | 1 | -34/+36 |
| | | | | | | | The ATX specification allows up to 500ms for the ATX power good signal to be asserted after power on request Extend time from power on request to fault condition set to about 800ms in order to ensure that PSUs close to the specification margins do not induce spurious faults. | ||||
* | Update BMC reset logicv1.05 | Raptor Engineering Development Team | 2018-04-26 | 1 | -3/+3 |
| | | | | Reset now attempted after 30 seconds of failure to exit U-boot | ||||
* | Fix BMC watchdog | Raptor Engineering Development Team | 2018-04-23 | 2 | -60/+83 |
| | | | | | | Debounce ATX power good to work around certain Delta PSUs asserting PG before rails can be loaded Initialize various registers to 0 to save die area Bump version number for further development | ||||
* | Wire second debug jumper as VGA disable, and expose value to hostv1.04 | Raptor Engineering Development Team | 2018-04-14 | 2 | -5/+4 |
| | | | | Bump revision number reported to 0x07 | ||||
* | Fix BMC-initiated error clear | Raptor Engineering Development Team | 2018-04-11 | 1 | -2/+2 |
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* | Add BMC startup watchdogv1.03 | Raptor Engineering Development Team | 2018-03-07 | 1 | -1/+23 |
| | | | | This works around ASpeed fast blink boot hang errata (app note #3) | ||||
* | Add LED override readbackv1.02 | Raptor Engineering Development Team | 2018-02-19 | 1 | -0/+3 |
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* | Add manufacturing fault trace logic for power sequencing | Raptor Engineering Development Team | 2018-02-13 | 1 | -6/+22 |
| | | | | Explicitly call out register addresses | ||||
* | Enhance front panel LED compatibility with SuperMicro chassis optionsv1.01 | Raptor Engineering Development Team | 2018-01-28 | 1 | -6/+21 |
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* | Add pullup on FlexVer™ reset linev1.00 | Raptor Engineering Development Team | 2018-01-23 | 1 | -2/+12 |
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* | Separate BMC status and chassis reset request lines | Raptor Engineering Development Team | 2018-01-22 | 2 | -16/+8 |
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* | Remove DD1 VCS overcurrent bug hack | Raptor Engineering Development Team | 2018-01-22 | 2 | -11/+1 |
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* | Add I2C write capability | Raptor Engineering Development Team | 2018-01-19 | 3 | -7/+63 |
| | | | | Add front panel LED override | ||||
* | Switch U-Boot phase indicators to staggered fader | Raptor Engineering Development Team | 2018-01-17 | 1 | -6/+37 |
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* | Indicate BMC boot phase as follows: | Raptor Engineering Development Team | 2018-01-17 | 1 | -6/+48 |
| | | | | | 1.) Initial power-on / U-Boot: KR pattern 2.) Kernel / userspace booting: fading pattern | ||||
* | Correct polarity of BMC boot complete signal | Raptor Engineering Development Team | 2018-01-17 | 2 | -9/+39 |
| | | | | Use fading startup pattern instead of prior KR pattern | ||||
* | Fix power rails not going offline on system shutdown | Raptor Engineering Development Team | 2018-01-17 | 1 | -2/+2 |
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* | Speed BMC boot pattern up somewhat | Raptor Engineering Development Team | 2018-01-17 | 1 | -2/+2 |
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* | Enable network link and activity LEDs on front and rear panel | Raptor Engineering Development Team | 2018-01-17 | 1 | -12/+77 |
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* | Expose power good/enable busses to I2C for debugging and diagnostic purposes | Raptor Engineering Development Team | 2018-01-16 | 1 | -0/+16 |
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* | Use open drain output on CPU standby reset line | Raptor Engineering Development Team | 2018-01-16 | 1 | -2/+15 |
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* | Take fan controller out of reset when BMC power good is established | Raptor Engineering Development Team | 2018-01-13 | 1 | -2/+2 |
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* | Convert combinatorial logic to registered logic to work around apparent ↵ | Raptor Engineering Development Team | 2018-01-12 | 3 | -113/+201 |
| | | | | | | | | | Yosys bug Add initial internal oscillator Fix license in PCF file Tested to work on initial Talos™ II hardware | ||||
* | Fix license template in Makefile | Raptor Engineering Development Team | 2018-01-07 | 1 | -3/+20 |
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* | Add vendor ID registers | Raptor Engineering Development Team | 2017-12-31 | 1 | -3/+22 |
| | | | | Add CPU1 presence detect to response field | ||||
* | Properly generate programming file | Raptor Engineering Development Team | 2017-12-30 | 1 | -2/+2 |
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* | Add initial Talos™ II front panel control logic | Raptor Engineering Development Team | 2017-12-30 | 3 | -15/+128 |
| | | | | Add initial Talos™ II system control logic | ||||
* | Remove spurious power_sequencer.v file | Raptor Engineering Development Team | 2017-12-30 | 2 | -224/+2 |
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* | Initial buildable variant for Talos™ II | Raptor Engineering Development Team | 2017-12-30 | 6 | -621/+847 |
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* | Initial conversion pass VHDL to Verilog | Raptor Engineering Development Team | 2017-12-29 | 9 | -1603/+1038 |
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* | Prepare files for Talos™ II modifications | Raptor Engineering Development Team | 2017-12-29 | 3 | -130/+130 |
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* | Initial import of Romulus support files | IBM | 2017-12-29 | 4 | -0/+1603 |