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authorRaptor Engineering Development Team <support@raptorengineering.com>2019-03-14 16:00:11 -0500
committerRaptor Engineering Development Team <support@raptorengineering.com>2019-03-14 16:00:11 -0500
commit14ad067f65b45558a513879cf64e039b2212843c (patch)
treea7020b2127bdb8220fce9b9f90bcb836d4a21af7
parent819d0eb720549fc34a0c9f2a34946fdca04a6a32 (diff)
downloadtalos-system-fpga-14ad067f65b45558a513879cf64e039b2212843c.zip
talos-system-fpga-14ad067f65b45558a513879cf64e039b2212843c.tar.gz
Add initial pre-PAR simulation framework from internal files
-rw-r--r--Makefile19
-rw-r--r--main.v12
-rw-r--r--testbench.v128
3 files changed, 150 insertions, 9 deletions
diff --git a/Makefile b/Makefile
index de4a43a..fdd5a29 100644
--- a/Makefile
+++ b/Makefile
@@ -1,6 +1,6 @@
# This file is part of the Talos™ II system FPGA implementation
#
-# © 2017 - 2018 Raptor Engineering, LLC
+# © 2017 - 2019 Raptor Engineering, LLC
# All Rights Reserved
#
# Redistribution and use in source and binary forms, with or without modification,
@@ -25,6 +25,8 @@
MAX_FPGA_ROUTE_PASSES = 100
+SOURCE_FILES = main.v i2c_slave.v
+
# Default seed
#ARACHNE_PNR_SEED = 1
@@ -84,8 +86,8 @@ endif
system_fpga.ex: system_fpga.int
icebox_explain system_fpga.int > system_fpga.ex
-system_fpga.blif: main.v i2c_slave.v
- yosys -l yosys.log -q -p "synth_ice40 -top system_fpga_top -blif system_fpga.blif" main.v i2c_slave.v
+system_fpga.blif: $(SOURCE_FILES)
+ yosys -l yosys.log -q -p "synth_ice40 -top system_fpga_top -blif system_fpga.blif" $(SOURCE_FILES)
system_fpga.bin: system_fpga.int
icepack system_fpga.int system_fpga.bin
@@ -97,6 +99,17 @@ system_fpga.rom: blank.rom system_fpga.bin
cp blank.rom system_fpga.rom
dd if=system_fpga.bin of=system_fpga.rom conv=notrunc
+system_fpga_test.vcd: $(SOURCE_FILES) testbench.v
+ rm -f system_fpga_sim
+ rm -f system_fpga.vcd
+ /usr/bin/iverilog -DSIMULATION -o system_fpga_sim $(SOURCE_FILES) testbench.v
+ ./system_fpga_sim
+
+simulate: system_fpga_test.vcd
+
+simulate_view: system_fpga_test.vcd
+ gtkwave system_fpga_test.vcd
+
all: system_fpga.rom
dump_toolchain_info:
diff --git a/main.v b/main.v
index 07ae362..43f8667 100644
--- a/main.v
+++ b/main.v
@@ -59,8 +59,8 @@ module system_fpga_top
// Second CPU presence detect
input wire cpub_present_l,
- output wire cpub_clk_oea,
- output wire cpub_clk_oeb,
+ output reg cpub_clk_oea,
+ output reg cpub_clk_oeb,
// Resets
output reg lpc_rst,
@@ -75,7 +75,7 @@ module system_fpga_top
output reg window_open_n,
// BMC system reset signalling
- inout bmc_system_reset_request_n,
+ output reg bmc_system_reset_request_n,
// Component disable lines
output reg pmc_disable_n,
@@ -290,9 +290,9 @@ module system_fpga_top
reg [7:0] i2c_write_reg_latch = 0;
// Front panel control signals
- wire panel_nic1_led_cathode_std;
- wire panel_nic2_led_cathode_std;
- wire panel_uid_led_std;
+ reg panel_nic1_led_cathode_std;
+ reg panel_nic2_led_cathode_std;
+ reg panel_uid_led_std;
reg [2:0] bmc_startup_kr = 3'b000;
reg [2:0] bmc_startup_fader = 3'b000;
reg [2:0] bmc_startup_staggered_fader = 3'b000;
diff --git a/testbench.v b/testbench.v
new file mode 100644
index 0000000..eae5488
--- /dev/null
+++ b/testbench.v
@@ -0,0 +1,128 @@
+// This file is part of the Talos™ II system FPGA implementation
+//
+// © 2017 - 2019 Raptor Engineering, LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Affero General Public License as
+// published by the Free Software Foundation, either version 3 of the
+// License, or (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU Affero General Public License for more details.
+//
+// You should have received a copy of the GNU Affero General Public License
+// along with this program. If not, see <https://www.gnu.org/licenses/>.
+
+`timescale 1ns / 100ps
+
+// Behavioral definition of SB_IO primitive
+module SB_IO (
+ inout PACKAGE_PIN,
+ input wire OUTPUT_ENABLE,
+ input wire D_OUT_0,
+ output wire D_IN_0,
+ input wire CLOCK_ENABLE,
+ input wire INPUT_CLK,
+ input wire OUTPUT_CLK
+ );
+
+ parameter PIN_TYPE = 0;
+ parameter PULLUP = 0;
+ parameter NEG_TRIGGER = 0;
+
+ reg registered_pin;
+ reg registered_output_pin;
+ wire input_clk_internal;
+ wire output_clk_internal;
+
+ assign input_clk_internal = (NEG_TRIGGER == 0) ? INPUT_CLK : ~INPUT_CLK;
+ assign output_clk_internal = (NEG_TRIGGER == 0) ? OUTPUT_CLK : ~OUTPUT_CLK;
+ always @(posedge input_clk_internal) begin
+ registered_pin <= PACKAGE_PIN;
+ end
+ always @(posedge output_clk_internal) begin
+ registered_output_pin <= D_OUT_0;
+ end
+
+ assign PACKAGE_PIN = (OUTPUT_ENABLE) ? ((PIN_TYPE[5:2] == 4'b1101) ? registered_output_pin : D_OUT_0) : 1'bz;
+ assign D_IN_0 = (PIN_TYPE[1:0] == 2'b01) ? PACKAGE_PIN : registered_pin;
+
+endmodule
+
+// Behavioral definition of SB_GB_IO primitive
+module SB_GB_IO (
+ inout PACKAGE_PIN,
+ input wire OUTPUT_ENABLE,
+ input wire D_OUT_0,
+ output wire GLOBAL_BUFFER_OUTPUT
+ );
+
+ parameter PIN_TYPE = 0;
+ parameter PULLUP = 0;
+
+ assign PACKAGE_PIN = (OUTPUT_ENABLE) ? D_OUT_0 : 1'bz;
+ assign GLOBAL_BUFFER_OUTPUT = PACKAGE_PIN;
+
+endmodule
+
+// Behavioral definition of SB_GB primitive
+module SB_GB (
+ input wire USER_SIGNAL_TO_GLOBAL_BUFFER,
+ output wire GLOBAL_BUFFER_OUTPUT
+ );
+
+ assign GLOBAL_BUFFER_OUTPUT = USER_SIGNAL_TO_GLOBAL_BUFFER;
+
+endmodule
+
+// Behavioral definition of SB_PLL40_CORE primitive
+module SB_PLL40_CORE (
+ output wire LOCK,
+ input wire RESETB,
+ input wire BYPASS,
+ input wire REFERENCECLK,
+ input wire LATCHINPUTVALUE,
+ output wire PLLOUTCORE,
+ output wire PLLOUTGLOBAL
+ );
+
+ parameter FEEDBACK_PATH = 0;
+ parameter PLLOUT_SELECT = 0;
+ parameter DIVR = 0;
+ parameter DIVF = 0;
+ parameter DIVQ = 0;
+ parameter FILTER_RANGE = 0;
+ parameter ENABLE_ICEGATE = 0;
+
+ assign PLLOUTCORE = REFERENCECLK;
+ assign PLLOUTGLOBAL = REFERENCECLK;
+
+endmodule
+
+// Main testbench
+module system_fpga_test();
+ reg lpc_clock;
+
+ wire cpub_clk_oea;
+ wire cpub_clk_oeb;
+
+ system_fpga_top U1(
+ .lpc_clock(lpc_clock),
+
+ .cpub_clk_oea(cpub_clk_oea),
+ .cpub_clk_oeb(cpub_clk_oeb)
+ );
+
+ initial begin
+ $dumpfile("system_fpga_test.vcd"); // Dumpfile
+ $dumpvars; // Dump all signals
+ end
+
+ always
+ #15 lpc_clock = ~lpc_clock; // Main 33MHz clock (approximated)
+
+ initial
+ #3000 $finish; // Terminate after 3µs
+endmodule
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