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authorRaptor Engineering Development Team <support@raptorengineering.com>2018-05-13 18:56:02 -0500
committerRaptor Engineering Development Team <support@raptorengineering.com>2018-05-13 18:56:47 -0500
commit55efaf2f8de05c513247fa90e12f7ca1a4805a0d (patch)
tree532c59a33570bfee395605b904edc49f532901f7
parent93a9aa88c653f278dd80c2915c77975e12fbe8eb (diff)
downloadtalos-system-fpga-55efaf2f8de05c513247fa90e12f7ca1a4805a0d.zip
talos-system-fpga-55efaf2f8de05c513247fa90e12f7ca1a4805a0d.tar.gz
Remove ATX power good filtering logicv1.06
ATX PG must remain high for minimum periods according to the specification Don't try to work around faulty external power supply designs
-rw-r--r--main.v24
1 files changed, 1 insertions, 23 deletions
diff --git a/main.v b/main.v
index 0822d49..32df956 100644
--- a/main.v
+++ b/main.v
@@ -227,7 +227,6 @@ module system_fpga_top
wire stdby_sed = 1'b0;
reg sysen_buf = 1'b0;
reg atx_force_enable = 1'b0;
- reg atx_pg_filtered = 1'b0;
reg atx_en_lockout = 1'b0;
parameter railarray_0 = {RAIL_SIZE{1'b0}};
parameter railarray_1 = {RAIL_SIZE{1'b1}}; // synchronizing signals
@@ -872,7 +871,7 @@ module system_fpga_top
// Assign Ports to PGood buffer
always @(posedge clk_in) begin
- pg_buf[0] = atx_pg_filtered;
+ pg_buf[0] = atx_pg;
pg_buf[1] = miscio_pg;
pg_buf[2] = vdna_pg;
pg_buf[3] = vdnb_pg | (cpub_present_n & en_buf[3]);
@@ -911,27 +910,6 @@ module system_fpga_top
en_buf[14] = (sysen_s2 & delay_done[13]) & ~err_found;
end
- // PSU startup sequencing logic
- reg [1:0] atx_pg_counter = 0;
- reg atx_pg_prev = 0;
- always @(posedge timer_clk_4) begin
- if (sysen_s2 | pg_s2[1]) begin
- if (atx_pg) begin
- atx_pg_counter <= atx_pg_counter + 1;
- if (atx_pg_counter > 2) begin
- atx_pg_filtered <= 1'b1;
- end
- end else begin
- atx_pg_filtered <= 1'b0;
- atx_pg_counter <= 0;
- end
- end else begin
- atx_pg_counter = 0;
- end
-
- atx_pg_prev <= atx_pg;
- end
-
// ERR state reset
always @(posedge clk_in) begin
clear_err = i2c_clr_err | host_clr_err;
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