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authorRaptor Engineering Development Team <support@raptorengineering.com>2019-04-30 04:37:23 +0000
committerRaptor Engineering Development Team <support@raptorengineering.com>2019-04-30 07:27:06 +0000
commitdf7e808365f0cbb8175f7f634dc9bc7a3e3a7443 (patch)
tree8cbec4791bb714d7253006fcd0df03e55c76fcc2
parentffa5a253cf1c238f037f57e6ab8f8a8c8a14c989 (diff)
downloadtalos-system-fpga-df7e808365f0cbb8175f7f634dc9bc7a3e3a7443.zip
talos-system-fpga-df7e808365f0cbb8175f7f634dc9bc7a3e3a7443.tar.gz
Use onboard oscillator on PCB revision 1.01 and higher
This breaks compatibility with PCB revision 1.00
-rw-r--r--main.v54
-rw-r--r--system_fpga.pcf7
2 files changed, 21 insertions, 40 deletions
diff --git a/main.v b/main.v
index 43f8667..699452a 100644
--- a/main.v
+++ b/main.v
@@ -1,11 +1,18 @@
// Copyright © 2017, International Business Machines Corp.
-// Copyright © 2017 - 2018 Raptor Engineering, LLC
+// Copyright © 2017 - 2019 Raptor Engineering, LLC
// All Rights Reserved
//
// See LICENSE file for licensing details
+//
+// HARDWARE ERRATA NOTICE
+// This version of the system FPGA will only function on hardware revision 1.01 or higher.
+// If you have hardware revision 1.00, please use the talos-pcb-rev1.00 branch instead!
module system_fpga_top
(
+ // FPGA clock
+ input wire fpga_clock,
+
// LPC clock
input wire lpc_clock,
@@ -232,7 +239,7 @@ module system_fpga_top
reg [RAIL_SIZE - 1:0] pg_buf = 0;
reg sysgood_buf = 1'b0;
wire clk_in;
- wire clk_in_lpc;
+ wire clk_in_fpga;
wire clk_in_ring;
wire stdby_sed = 1'b0;
reg sysen_buf = 1'b0;
@@ -302,41 +309,14 @@ module system_fpga_top
reg hostboot_startup_fader_common_high = 1'b0;
reg [7:0] led_override_request = 8'b00000000;
- // Implement nasty ring oscillator for fallback use when main system clock is offline
- // Thanks to Clifford Wolf for the idea and basic code!
- wire chain_in;
- wire chain_out;
- wire [99:0] buffers_in;
- wire [99:0] buffers_out;
- assign buffers_in = {buffers_out[98:0], chain_in};
- assign chain_out = buffers_out[99];
- assign chain_in = !chain_out;
-
- SB_LUT4 #(
- .LUT_INIT(16'd2)
- ) buffers [99:0] (
- .O(buffers_out),
- .I0(buffers_in),
- .I1(1'b0),
- .I2(1'b0),
- .I3(1'b0)
- );
-
- // Divide unstable 10MHz ring clock down to ~2MHz
- reg [2:0] ring_clock_divider = 0;
- always @(posedge chain_out) begin
- ring_clock_divider = ring_clock_divider + 1;
+ // Divide input 8MHz clock down to 1MHz
+ reg [2:0] fpga_clock_divider = 0;
+ always @(posedge fpga_clock) begin
+ fpga_clock_divider = fpga_clock_divider + 1;
end
- assign clk_in_ring = ring_clock_divider[2];
+ assign clk_in_fpga = fpga_clock_divider[2];
- // Divide input 33MHz clock down to 4.125MHz
- reg [2:0] lpc_clock_divider = 0;
- always @(posedge lpc_clock) begin
- lpc_clock_divider = lpc_clock_divider + 1;
- end
- assign clk_in_lpc = lpc_clock_divider[2];
-
- // Divide 4.125MHz clock down to 500Hz, 125Hz, and 7Hz, respectively
+ // Divide 4MHz clock down to 488Hz, 122Hz, and 6Hz, respectively
wire timer_clk_2;
wire timer_clk_3;
wire timer_clk_4;
@@ -348,9 +328,7 @@ module system_fpga_top
assign timer_clk_3 = timer_clk_counter[14];
assign timer_clk_4 = timer_clk_counter[16];
- reg clock_select = 1'b1;
-
- assign clk_in = (clock_select)?clk_in_ring:clk_in_lpc;
+ assign clk_in = clk_in_fpga;
// I2C device
i2c_slave #(
diff --git a/system_fpga.pcf b/system_fpga.pcf
index 2beb0f1..3a5b23b 100644
--- a/system_fpga.pcf
+++ b/system_fpga.pcf
@@ -1,6 +1,6 @@
# This file is part of the Talos™ II system FPGA implementation
#
-# © 2017 - 2018 Raptor Engineering, LLC
+# © 2017 - 2019 Raptor Engineering, LLC
# All Rights Reserved
#
# Redistribution and use in source and binary forms, with or without modification,
@@ -26,6 +26,9 @@
# Intended for use with Talos™ II systems from Raptor Computing Systems, LLC
# https://www.raptorcs.com/TALOSII
+# FPGA clock
+set_io fpga_clock 81
+
# LPC clock
set_io lpc_clock 13
@@ -120,4 +123,4 @@ set_io panel_uid_led 89
# Front panel switches
set_io panel_reset_in_l 73
-set_io flexver_reset_in_l 74 \ No newline at end of file
+set_io flexver_reset_in_l 74
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