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* P9: NVDIMM SBE Support to Trigger Catastrophic SaveTsung Yeung2019-01-112-2/+24
* Mark OB1 and OB2 present for AxoneSantosh Puranik2019-01-101-1/+2
* Change target types to 64-bit and add P10 target typesThi Tran2019-01-102-63/+73
* Initial mss_field endian modificationAndre Marin2019-01-101-3/+3
* Adds explorer OMI training codeStephen Glancy2019-01-101-2/+12
* Implement exp_check_for_readyAndre Marin2019-01-101-0/+19
* Added I2C fields, EXP_FW_STATUS APIAndre Marin2019-01-091-0/+132
* Add empty explorer "check_for_ready" procedure filesAndre Marin2019-01-091-0/+24
* Flush NVDIMM ChipopSunil Kumar2019-01-078-7/+168
* apply HW423589 option1 (MCD disable) workaround for p9n DD2.1Joe McGill2018-12-172-18/+12
* Move MNFG_TEST_ALL_SPARE_DRAM_ROWS to a new encodingLouis Stermole2018-12-171-2/+2
* Enable Nimbus DD23 risk levelsJenny Huynh2018-12-171-10/+100
* Fix i2c doxy and update i2c_access.H doxy to match fapi2_access_i2c.HAndre Marin2018-12-171-2/+2
* fapi2 i2c dox updateMatt K. Light2018-12-171-0/+25
* fapi2 i2c access headersMatt K. Light2018-12-171-0/+71
* Fixes LRDIMM eff_config bugsStephen Glancy2018-12-171-0/+60
* Removes unused attribute accessorsStephen Glancy2018-12-171-91/+0
* Default DDR4-2933 to 2666Tsung Yeung2018-12-171-1/+2
* Updates the training advanced algorithmStephen Glancy2018-12-171-2/+28
* Change ATTR_MSS_WR_VREF_OFFSET to be override-onlyDan Crowell2018-12-171-1/+3
* Updates custom RD CTR patternStephen Glancy2018-12-171-4/+4
* Updates training advanced and adds custom WR CTRStephen Glancy2018-12-171-4/+26
* Updates WR VREF for characterization resultsStephen Glancy2018-12-171-0/+13
* Add Write CRC attributes to xml and eff_dimmAndre Marin2018-12-171-0/+15
* Disabled Training Advance in simJacob Harvey2018-12-171-2/+0
* Implementing draminit_training_advJacob Harvey2018-12-171-7/+41
* Add in L1 draminit_training_adv filesJacob Harvey2018-12-171-0/+19
* Improve description of ATTR_EFF_RANK_GROUP_OVERRIDELouis Stermole2018-12-171-5/+13
* Remove ZQCAL redundant CCS inst, move to draminit_trainingAndre Marin2018-12-171-14/+30
* Add PHY sequencer refresh settings after draminitAndre Marin2018-12-171-0/+16
* Fix up setup_cal and vref attrsJacob Harvey2018-12-171-0/+15
* Disable RTT_WR during WR_LEVEL cal step, and set equivalent terminationsLouis Stermole2018-12-171-0/+16
* Add attribute ATTR_EFF_RANK_GROUP_OVERRIDELouis Stermole2018-12-171-0/+17
* Fixing raw card setting for DIMMsJacob Harvey2018-12-171-14/+14
* Updates MCBIST for dual-drop systemsStephen Glancy2018-12-171-0/+15
* Disabling temp_refresh_modeJacob Harvey2018-12-171-19/+0
* Add MSS customization support from CRP0 Lx MVPDJoe McGill2018-12-171-2/+16
* Move MRS attributes to eff_config to calc LRDIMMsJacob Harvey2018-12-171-0/+46
* Add read cmd, precharge all cmd, and read cmd CCS instruction and unit testsAndre Marin2018-12-171-1/+1
* Fixing bulk_pwr_throttles calculationsJacob Harvey2018-12-171-1/+14
* Add LRDIMM to translation register infrastructure and unit tests.Andre Marin2018-12-171-19/+28
* Enable read VREF calibrationBrian Silver2018-12-171-1/+1
* Add DP16 workarounds for Nimbus DD1.0Brian Silver2018-12-171-0/+36
* Implement L2 eff_config_thermal, bulk_pwr_throttleJacob Harvey2018-12-171-4/+19
* Fixed CL and timing bugs, unit test augmentationsStephen Glancy2018-12-171-9/+36
* Started implementation of bulk_pwr_throttlesJacob Harvey2018-12-171-58/+2
* Add disabled bit processing for DDR PHY initial calibrationBrian Silver2018-12-171-0/+15
* Change p9_mss_freq_system to write attributes, errors for CronusBrian Silver2018-12-171-16/+0
* Add an attribute to avoid the plug rules in partial good scenariosBrian Silver2018-12-171-0/+15
* Cleaned spd xml and Added module manufacturer infoJacob Harvey2018-12-171-11/+0
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