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| author | Joe McGill <jmcgill@us.ibm.com> | 2018-12-12 09:04:44 -0600 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-12-17 21:18:11 -0600 |
| commit | 658b2f4ef5f3057b1c7ea0cf0a0fa7579451a81e (patch) | |
| tree | 39470128144b673fe6c8f4c8b45893d58871ce38 /src | |
| parent | 9dc84acf36930c8ea4c97a40e9e22a0b240a9b12 (diff) | |
| download | talos-sbe-658b2f4ef5f3057b1c7ea0cf0a0fa7579451a81e.tar.gz talos-sbe-658b2f4ef5f3057b1c7ea0cf0a0fa7579451a81e.zip | |
apply HW423589 option1 (MCD disable) workaround for p9n DD2.1
Current FW uses option2 (alternate MCD configuration) to workaround
HW423589 for p9n DD2.1 hardware, which is desired for OP releases
supporting GPUs.
This commit adjusts the DD2.1 solution to option1 instead,
and can be cherry-picked into the enterprise release branches to
remove the per-socket memory resrictions which come as a side effect
of the current option2 setup.
Change-Id: I24ecf918a81964a3df6b1e3e18e60375d7646b45
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69718
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69845
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C | 16 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 14 |
2 files changed, 12 insertions, 18 deletions
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C index 9dc5e63c..8e7cb7ce 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C @@ -124,29 +124,29 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<8, 3, 61, uint64_t>(literal_0x3 ); } - if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) - && (l_chip_ec == 0x23)) ) + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) + && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) ) { constexpr auto l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_WR_DISABLE_GROUP_ON = 0x1; l_scom_buffer.insert<1, 1, 63, uint64_t>(l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_WR_DISABLE_GROUP_ON ); } - if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) - && (l_chip_ec == 0x23)) ) + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) + && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) ) { constexpr auto l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_RD_DISABLE_GROUP_ON = 0x1; l_scom_buffer.insert<5, 1, 63, uint64_t>(l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_RD_DISABLE_GROUP_ON ); } - if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) - && (l_chip_ec == 0x23)) ) + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) + && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) ) { constexpr auto l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_WR_DISABLE_VG_NOT_SYS_ON = 0x1; l_scom_buffer.insert<2, 1, 63, uint64_t>(l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_WR_DISABLE_VG_NOT_SYS_ON ); } - if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) - && (l_chip_ec == 0x23)) ) + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) + && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) ) { constexpr auto l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_RD_DISABLE_VG_NOT_SYS_ON = 0x1; l_scom_buffer.insert<6, 1, 63, uint64_t>(l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_RD_DISABLE_VG_NOT_SYS_ON ); diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 6e55904e..6925a3b8 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -7600,13 +7600,14 @@ <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> Enable extended addressing mode to workaround MCD - coherency issue HW423589 + coherency issue HW423589. EC update will prevent application on + any system. </description> <chipEcFeature> <chip> <name>ENUM_ATTR_NAME_NIMBUS</name> <ec> - <value>0x21</value> + <value>0xAF</value> <test>EQUAL</test> </ec> </chip> @@ -7615,7 +7616,7 @@ <!-- ******************************************************************** --> <attribute> <id>ATTR_CHIP_EC_FEATURE_HW423589_OPTION1</id> - <targetType>TARGET_TYPE_PROC_CHIP,TARGET_TYPE_PROC_CHIP</targetType> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> Disable MCD to workaround coherency issue HW423589 </description> @@ -7624,13 +7625,6 @@ <name>ENUM_ATTR_NAME_NIMBUS</name> <ec> <value>0x20</value> - <test>EQUAL</test> - </ec> - </chip> - <chip> - <name>ENUM_ATTR_NAME_NIMBUS</name> - <ec> - <value>0x22</value> <test>GREATER_THAN_OR_EQUAL</test> </ec> </chip> |
