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| author | Stephen Glancy <sglancy@us.ibm.com> | 2018-10-22 21:33:27 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-12-17 21:16:03 -0600 |
| commit | f97b07db36ea6051e41e9071577ae9045b0cd964 (patch) | |
| tree | 8d824e85b2cb0bc34190b860c54979502d0ad3e4 /src | |
| parent | 88910edf281ae36d2410713180b5e711c4b84006 (diff) | |
| download | talos-sbe-f97b07db36ea6051e41e9071577ae9045b0cd964.tar.gz talos-sbe-f97b07db36ea6051e41e9071577ae9045b0cd964.zip | |
Fixes LRDIMM eff_config bugs
Change-Id: I74dd2332bda79ab9578d450ba74322fd953b1f46
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67863
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69816
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml index 3f6aa7c1..45752794 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml @@ -2409,6 +2409,7 @@ <valueType>uint8</valueType> <writeable /> <array> 2 2 </array> + <mssAccessorName>eff_dimm_ddr4_bc06</mssAccessorName> </attribute> <attribute> @@ -2518,6 +2519,7 @@ <valueType>uint8</valueType> <writeable /> <array> 2 2 </array> + <mssAccessorName>eff_dimm_ddr4_f0bc1x</mssAccessorName> </attribute> <attribute> @@ -2568,6 +2570,7 @@ <valueType>uint8</valueType> <writeable /> <array> 2 2 </array> + <mssAccessorName>eff_dimm_ddr4_f0bc6x</mssAccessorName> </attribute> <attribute> @@ -2698,6 +2701,17 @@ </attribute> <attribute> + <id>ATTR_EFF_DIMM_DDR4_F2BCEx</id> + <targetType>TARGET_TYPE_MCS</targetType> + <description>F2BCWEx Host Interface DFE Programming Control Word</description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable /> + <array> 2 2 </array> + <mssAccessorName>eff_dimm_ddr4_f2bcex</mssAccessorName> + </attribute> + + <attribute> <id>ATTR_EFF_DIMM_DDR4_F4BC0x</id> <targetType>TARGET_TYPE_MCS</targetType> <description>F4BCW0x MRS0 snooped settings</description> @@ -2815,6 +2829,7 @@ <valueType>uint8</valueType> <writeable /> <array> 2 2 </array> + <mssAccessorName>eff_dimm_ddr4_f5bc5x</mssAccessorName> </attribute> <attribute> @@ -3004,6 +3019,51 @@ </attribute> <attribute> + <id>ATTR_EFF_DRAM_ODIC</id> + <targetType>TARGET_TYPE_MCS</targetType> + <description> + DRAM output driver impedance control (ODIC) + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>OHM34 = 34, OHM48 = 48</enum> + <writeable/> + <array> 2 2 4 </array> + <mssAccessorName>eff_dram_odic</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MSS_EFF_ODT_RD</id> + <targetType>TARGET_TYPE_MCS</targetType> + <description> + READ, On Die Termination triggering bitmap. Use bitmap to determine which ODT to fire for the designated rank. + The bits in 8 bit field are [Dimm0 ODT0][Dimm0 ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 ODT1][N/A][N/A] + Attribute is derived from VPD for RDIMM or from termination settings for LRDIMM + </description> + <initToZero></initToZero> + <writeable/> + <valueType>uint8</valueType> + <mssAccessorName>eff_odt_rd</mssAccessorName> + <array>2 2 4</array> + </attribute> + + <attribute> + <id>ATTR_MSS_EFF_ODT_WR</id> + <targetType>TARGET_TYPE_MCS</targetType> + <description> + WRITE, On Die Termination triggering bitmap. Use bitmap to determine which ODT to fire for the designated rank. + The bits in 8 bit field are [Dimm0 ODT0][Dimm0 ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 ODT1][N/A][N/A] + Attribute is derived from VPD for RDIMM or from termination settings for LRDIMM + </description> + <initToZero></initToZero> + <writeable/> + <valueType>uint8</valueType> + <writeable/> + <mssAccessorName>eff_odt_wr</mssAccessorName> + <array>2 2 4</array> + </attribute> + + <attribute> <id>ATTR_EFF_DRAM_TREFI</id> <targetType>TARGET_TYPE_MCS</targetType> <description> |
