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* p9_sbe_chiplet_pll_setup optimizedAnusha Reddy Rangareddygari2017-01-181-162/+111
* SGPE HWP : tune PFET controller pollingAmit Kumar2017-01-171-2/+7
* p9_sbe_chiplet_reset -- drive PCIE PLL from SS filter PLL for DD1.xJoe McGill2017-01-172-6/+32
* PK stack checkingDoug Gilbert2017-01-175-9/+50
* tpm reset supportSachin Gupta2017-01-171-10/+72
* add SS PLL settings to support 94 MHz PCI operationJoe McGill2017-01-161-0/+18
* Modify signature of p9_stopclocksspashabk-in2017-01-162-70/+99
* p9_stopclocks SBE/PPE related changesspashabk-in2017-01-164-31/+205
* Implementation of PIB stopclock with CBSSoma BhanuTej2017-01-164-51/+231
* Adding bool for cache/cores in the p9_stopclocks HWPSoma BhanuTej2017-01-162-9/+25
* Changing ATTR_PG from 32 to 16 bitAnusha Reddy Rangareddygari2017-01-161-3/+3
* Stopclock procedure updatesSoma BhanuTej2017-01-164-56/+110
* Fixing a bug in stopclk cmn module - p9_common_stopclocksSoma BhanuTej2017-01-162-3/+3
* Fapi Implementation of Level2 HWP p9_stopclocksSoma BhanuTej2017-01-1610-19/+1060
* Level 1 HWP for p9_stopclocksSoma BhanuTej2017-01-162-0/+150
* configure FBC pump mode in SBEJoe McGill2017-01-158-118/+95
* p9_getecid -- set PCIE DD1.0x workaround attributesJoe McGill2017-01-151-0/+34
* Add new core workarounds, defect inline in the initfileNick Klazynski2017-01-131-3/+3
* Specialization of getParent for compound targetsSantosh Puranik2017-01-123-12/+70
* Timer serviceSachin Gupta2017-01-1114-7/+739
* SW375288: Reads to C_RAS_MODEREG causes SPR corruptionNick Klazynski2017-01-111-13/+19
* Enabled Put/Get Scom tracesRaja Das2017-01-111-4/+7
* Enable imprecise mode only for CMEPrasad Bg Ranganath2017-01-101-2/+0
* Enable QUEUED SCAN in CME putring codePrasad Bg Ranganath2017-01-101-1/+3
* Update backing buildSachin Gupta2017-01-092-25/+25
* HW398189: mask SIBRC = 6 in CME MSR under NDD1Yue Du2017-01-082-2/+28
* Increasing delay for l3_flush based on HW requirementsCHRISTINA L. GRAVES2017-01-061-2/+2
* ISTEP4: using FAPI_ASSERT instead of manual fapi_rc_falseYue Du2017-01-041-38/+33
* Add MSS customization support from CRP0 Lx MVPDJoe McGill2017-01-042-36/+10
* Change MCFIR_CHANNEL_0_TIMEOUT_ERROR to be maskedBrian Silver2017-01-041-2/+1
* Security control override disable support - p9_setup_sbe_configSoma BhanuTej2017-01-041-19/+1
* p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2017-01-042-18/+27
* Hcode: add a new xml error fileYue Du2017-01-042-1/+39
* Fix to continue with next core if HW errors are to be ignoredAmit Tendolkar2017-01-041-2/+2
* PK Support for 1.125 timebase scaleDoug Gilbert2017-01-031-6/+12
* p9.fbc.scan.initfile -- clock off MCSYNC staging latchesJoe McGill2017-01-011-0/+18
* HCODE: Drop TLBIE Quiesce after initfile scan it to 1Yue Du2016-12-201-2/+2
* HW396520: DD1 workaround skip flushmode inhibit drop in cache hwpYue Du2016-12-203-7/+34
* PM: Added support for CME/SGPE flags in respective image header.Prem Shanker Jha2016-12-201-0/+18
* Removed hw image patchSachin Gupta2016-12-201-2/+0
* Reverting RS4v3 changesSachin Gupta2016-12-209-927/+903
* TOR reduction: Ditching DeltaRingLayout and RingLayout_tClaus Michael Olsen2016-12-204-375/+313
* Shrinking RS4 headerMartin Peschke2016-12-207-528/+616
* IStep4: add check for partial good cores under given exYue Du2016-12-201-29/+38
* p9_tor: Fix the Instance ring tor offset in TOR layoutPrasad Bg Ranganath2016-12-201-26/+33
* update core internal/external hang timeoutsJoe McGill2016-12-202-1/+12
* Modify initCompiler to use template version of buffer insertRichard J. Knight2016-12-205-100/+100
* Modify initCompiler to use FAPI_TRY in generated proceduresRichard J. Knight2016-12-205-509/+80
* Update code to consolidate writes to same address in same putScomRichard J. Knight2016-12-205-1363/+478
* p9_hcd_cache_chiplet_reset skip entire vcs workaround in simBen Gass2016-12-201-99/+95
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