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authorYue Du <daviddu@us.ibm.com>2017-01-04 14:18:01 -0600
committerSachin Gupta <sgupta2m@in.ibm.com>2017-01-08 23:47:36 -0500
commit120eed7aa6f2d80b04240dcebde4cd3b42158d61 (patch)
tree7fbe8325a9517ce46039afe62bfc97f0a8c6e3ae /src
parent8f574bb53e1db2c8b92d58a40140a113a6f5f3a3 (diff)
downloadtalos-sbe-120eed7aa6f2d80b04240dcebde4cd3b42158d61.tar.gz
talos-sbe-120eed7aa6f2d80b04240dcebde4cd3b42158d61.zip
HW398189: mask SIBRC = 6 in CME MSR under NDD1
Change-Id: I19df802466d23c371b23971dce43a67ddc9cd60d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34373 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: ADAM S. HALE <ashale@us.ibm.com> Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com> Reviewed-by: JAMES DEZELLE <jdezelle@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34377 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src')
-rw-r--r--src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h20
-rw-r--r--src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_msr.h10
2 files changed, 28 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h
index 42f79df0..8b0783b2 100644
--- a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER sbe Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2016 */
+/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -299,13 +299,31 @@ popcount64(uint64_t x)
#if defined(USE_PPE_IMPRECISE_MODE)
+#if defined(MASK_MSR_SEM6)
+
+#define PK_THREAD_MACHINE_CONTEXT_DEFAULT \
+ (MSR_UIE | MSR_EE | MSR_ME | MSR_IS0 | MSR_IS1 | MSR_IS2 | MSR_IPE | MSR_SEM6)
+
+#else
+
#define PK_THREAD_MACHINE_CONTEXT_DEFAULT \
(MSR_UIE | MSR_EE | MSR_ME | MSR_IS0 | MSR_IS1 | MSR_IS2 | MSR_IPE)
+
+#endif /*MASK_MSR_SEM6*/
+
+#else
+
+#if defined(MASK_MSR_SEM6)
+
+#define PK_THREAD_MACHINE_CONTEXT_DEFAULT \
+ (MSR_UIE | MSR_EE | MSR_ME | MSR_IS0 | MSR_IS1 | MSR_IS2 | MSR_SEM6)
+
#else
#define PK_THREAD_MACHINE_CONTEXT_DEFAULT \
(MSR_UIE | MSR_EE | MSR_ME | MSR_IS0 | MSR_IS1 | MSR_IS2)
+#endif /*MASK_MSR_SEM6*/
#endif /*USE_PPE_IMPRECISE_MODE*/
#endif /*PK_THREAD_MACHINE_CONTEXT_DEFAULT*/
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_msr.h b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_msr.h
index 5af84f16..5fdbf314 100644
--- a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_msr.h
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_msr.h
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER sbe Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2016 */
+/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -57,6 +57,14 @@
#define MSR_SEM_START_BIT 1
#define MSR_SEM_LEN 7
+#define MSR_SEM1 0x40000000
+#define MSR_SEM2 0x20000000
+#define MSR_SEM3 0x10000000
+#define MSR_SEM4 0x08000000
+#define MSR_SEM5 0x04000000
+#define MSR_SEM6 0x02000000
+#define MSR_SEM7 0x01000000
+
#define MSR_SIBRC_START_BIT 9
#define MSR_SIBRC_LEN 3
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