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path: root/src/import/chips/p9/procedures/xml/attribute_info
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* Updates WR VREF for characterization resultsStephen Glancy2018-12-171-0/+13
* Add Write CRC attributes to xml and eff_dimmAndre Marin2018-12-171-0/+15
* Disabled Training Advance in simJacob Harvey2018-12-171-2/+0
* Implementing draminit_training_advJacob Harvey2018-12-171-7/+41
* Add in L1 draminit_training_adv filesJacob Harvey2018-12-171-0/+19
* Improve description of ATTR_EFF_RANK_GROUP_OVERRIDELouis Stermole2018-12-171-5/+13
* Remove ZQCAL redundant CCS inst, move to draminit_trainingAndre Marin2018-12-171-14/+30
* Add PHY sequencer refresh settings after draminitAndre Marin2018-12-171-0/+16
* Fix up setup_cal and vref attrsJacob Harvey2018-12-171-0/+15
* Disable RTT_WR during WR_LEVEL cal step, and set equivalent terminationsLouis Stermole2018-12-171-0/+16
* Add attribute ATTR_EFF_RANK_GROUP_OVERRIDELouis Stermole2018-12-171-0/+17
* Fixing raw card setting for DIMMsJacob Harvey2018-12-171-14/+14
* Updates MCBIST for dual-drop systemsStephen Glancy2018-12-171-0/+15
* Disabling temp_refresh_modeJacob Harvey2018-12-171-19/+0
* Add MSS customization support from CRP0 Lx MVPDJoe McGill2018-12-171-2/+16
* Move MRS attributes to eff_config to calc LRDIMMsJacob Harvey2018-12-171-0/+46
* Add read cmd, precharge all cmd, and read cmd CCS instruction and unit testsAndre Marin2018-12-171-1/+1
* Fixing bulk_pwr_throttles calculationsJacob Harvey2018-12-171-1/+14
* Add LRDIMM to translation register infrastructure and unit tests.Andre Marin2018-12-171-19/+28
* Enable read VREF calibrationBrian Silver2018-12-171-1/+1
* Add DP16 workarounds for Nimbus DD1.0Brian Silver2018-12-171-0/+36
* Implement L2 eff_config_thermal, bulk_pwr_throttleJacob Harvey2018-12-171-4/+19
* Fixed CL and timing bugs, unit test augmentationsStephen Glancy2018-12-171-9/+36
* Started implementation of bulk_pwr_throttlesJacob Harvey2018-12-171-58/+2
* Add disabled bit processing for DDR PHY initial calibrationBrian Silver2018-12-171-0/+15
* Change p9_mss_freq_system to write attributes, errors for CronusBrian Silver2018-12-171-16/+0
* Add an attribute to avoid the plug rules in partial good scenariosBrian Silver2018-12-171-0/+15
* Cleaned spd xml and Added module manufacturer infoJacob Harvey2018-12-171-11/+0
* Add bit field of master ranks attribute for PRDBrian Silver2018-12-171-0/+14
* Change PHY to use GPO, RLO, WLO from VPDBrian Silver2018-12-171-42/+0
* Modifying ATTRs for memory power thermalJacob Harvey2018-12-171-23/+55
* Implement MRW attributes; dram_clks, db_util, 2n_modeBrian Silver2018-12-171-15/+0
* Fix eff_config, remove custom_dimmJacob Harvey2018-12-171-39/+2
* Fixed eff_config attr generationStephen Glancy2018-12-171-1/+1
* Adding defaults for DRAM dll_reset and dll_enableLouis Stermole2018-12-171-1/+2
* Changes related to RTT VPD settingsBrian Silver2018-12-171-61/+1
* Add consumption of IBT from VPD and place in RCD7xBrian Silver2018-12-171-19/+0
* Change ODT R/W to take values from VPDBrian Silver2018-12-171-32/+0
* Change MSS_VOLT to MSS_VOLT_VDDRJacob Harvey2018-12-171-5/+5
* Fix p9_mss_utils_to_throttle, create throttles API, attribute cleanupAndre Marin2018-12-171-43/+16
* Modify SPD blob and eff-config hardcoding to match VBUAndre Marin2018-12-171-56/+0
* Packaging of memory vpd on Nimbus, MCA->MCSwhs2018-12-171-112/+0
* Added initToZero tag for all memory attributesJacob Harvey2018-12-171-0/+225
* Add eff_config functionality needed for RIT, fix cas_latency bug & attr filesAndre Marin2018-12-171-393/+36
* Add override attributes for memory vpd accessDan Crowell2018-12-171-0/+104
* Remove whitespace that breaks HB attribute compilerDan Crowell2018-12-171-1/+1
* Fix throttle procedure & MSS attribute clean upAndre Marin2018-12-171-2940/+178
* Add L2 p9_mss_scrubBrian Silver2018-12-171-348/+0
* Modify freq & dep. files. Add cas latency & unit testsAndre Marin2018-12-171-5/+7
* Add dp16 io tx dll/vreg configBrian Silver2018-12-171-0/+2
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