diff options
| author | Andre Marin <aamarin@us.ibm.com> | 2017-08-30 10:42:08 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-12-17 21:13:34 -0600 |
| commit | f83a56fc20e857fcf66cd4207cc799a1e1928353 (patch) | |
| tree | 2482ec9c4725595634f048dffce0b211284bf2aa /src/import/chips/p9/procedures/xml/attribute_info | |
| parent | cf118099b000c93126e66616e08158df94615463 (diff) | |
| download | talos-sbe-f83a56fc20e857fcf66cd4207cc799a1e1928353.tar.gz talos-sbe-f83a56fc20e857fcf66cd4207cc799a1e1928353.zip | |
Add Write CRC attributes to xml and eff_dimm
Added ATTR_EFF_PACKAGE_RANK_MAP, ATTR_EFF_NIBBLE_MAP, and
ATTR_MSS_EFF_WR_CRC attributes.
Change-Id: Ib665e22ce755282afb012ca0df9c670770fa1dd6
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45386
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Dev-Ready: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69808
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml/attribute_info')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml index b34bd399..e29d37cf 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml @@ -3251,6 +3251,21 @@ </attribute> <attribute> + <id>ATTR_MSS_EFF_WR_CRC</id> + <targetType>TARGET_TYPE_MCS</targetType> + <description> + Controls ENABLE/DISABLE of Write CRC + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <enum>DISABLE = 0, ENABLE = 1</enum> + <mssUnits> bool </mssUnits> + <array> 2 </array> + <mssAccessorName>eff_wr_crc</mssAccessorName> + </attribute> + + <attribute> <id>ATTR_MSS_PHY_SEQ_REFRESH</id> <targetType>TARGET_TYPE_MCS</targetType> <description> |
