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* HW399609: DD1 changing core/nest hang limit or hang pulse dividerYue Du2017-02-241-0/+4
| | | | | | | | | | | | | | Change-Id: I580cd70ce3315ea3f2aeb274279a89375f02b05d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36375 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36382 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Removing ATTR_PROC_FABRIC_ADDR_BAR_MODEThi Tran2017-02-211-4/+0
| | | | | | | | | | | | | | | | | | We only support Large system forward Change-Id: Id237e1bdbcb0d1eff34f74b348430df958bcc712 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36610 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36612 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Make ATTR_CHIP_UNIT_POS virtualSantosh Puranik2017-02-191-65/+2
| | | | | | | | | | | | | Change-Id: Ia88190cc391d3063c1afbef897e9135c15f29614 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35963 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35964 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Santosh S. Puranik <santosh.puranik@in.ibm.com>
* Workaround to fix issue where Powerbus loses track of EQs in DD1Raja Das2017-02-161-0/+4
| | | | | | | | | | | | | Change-Id: Ia7ffcfdead79e859f21b95be183af05949e68579 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36276 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36277 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* ATTR_CHIP_EC_FEATURE_CORE_TRACE_SCOMABLE attribute in SBEspashabk-in2017-02-031-0/+4
| | | | | | | | | | | Change-Id: Ic59654f7e0acd0daef7ec5b22ff6cdd06125eb07 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35884 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Martin Peschke <mpeschke@de.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35886 Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
* Control NDL training updateAnusha Reddy Rangareddygari2017-01-311-0/+4
| | | | | | | | | | | | | | Change-Id: I13d721d7fb1d71c58314dd1e09006a7b4df0dee2 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35211 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35216 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* VITAL cleaning for DD2Anusha Reddy Rangareddygari2017-01-241-5/+1
| | | | | | | | | | | | | | | | cq : HW399324 Change-Id: I4236b25b2587cb9705632dd55077c79e3d5cf246 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34827 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Abhishek Agarwal <abagarw8@in.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34828 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_tp_chiplet_init3 -- disable TP TOD hang pulseJoe McGill2017-01-241-0/+4
| | | | | | | | | | | | Change-Id: I838703170232b7ad39ae752f0fcde996f5bd577e CQ: HW401184 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35199 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35202 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Set plck as default mode in ATTR_BOOT_FLAGSSantosh Puranik2017-01-221-1/+1
| | | | | | | | | | | | Change-Id: I1f9f8a5db4a152efa719fac3c53a0150dfb43ccc Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35101 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35107 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* p9_sbe_chiplet_reset -- drive PCIE PLL from SS filter PLL for DD1.xJoe McGill2017-01-171-1/+5
| | | | | | | | | | | | | | | | | | | | | | | For DD1.0[123], to obtain Gen3 or Gen4 operation, we need to run the PCIE clocks at a slower speed. For simplicity we will just do this across the board for all DD1.0 parts. 34389 updates the SS filter PLL to output a reduced frequency output (94 MHz instead of 100 MHz nominal) for DD1 only. This commit will trigger the SBE to use the SS filter PLL to feed the downstream PCIE PLLs, for DD1 only. Change-Id: I344455de1fc54e9180090740b5725d580cb35b6f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34985 Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34996 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* HW396520: DD1 workaround skip flushmode inhibit drop in cache hwpYue Du2016-12-201-0/+4
| | | | | | | | | | | | | | | Change-Id: I6575ec51a94024708611678bee7af0cf7819b206 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33362 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com> Reviewed-by: ADAM S. HALE <ashale@us.ibm.com> Dev-Ready: ADAM S. HALE <ashale@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33366 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Remove unused SBE attributesSantosh Puranik2016-11-281-126/+1
| | | | | | | | | | | | | | | Change-Id: I9e7347b1508752bddf90d534edba27e0277b981d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32857 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32858 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* p9_sbe_lpc_init fix with GPIO resetCHRISTINA L. GRAVES2016-11-211-0/+4
| | | | | | | | | | | | Change-Id: I019d7ba16b4e39b5cf140fe1461218736ce329f5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32199 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32285 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_attr_setup updatesAnusha Reddy Rangareddygari2016-11-211-0/+4
| | | | | | | | | | | | | | | | | | | | | | set the ATTR_IS_SP_MODE attribute from MBX scratch reg 3 CQ : HW393961 Change-Id: Id1eb51173451680367de614c114bd0732a678e5b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32468 Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32469 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* Istep4: Enable poll for DPLL lock in p9_hcd_cache_dpll_setupYue Du2016-11-211-1/+4
| | | | | | | | | | | | | | | | | | | | | | | changes in this commit: 1) enable dpll lock checking in non-sim envrionment 2) change FAPI_DBG lines on set/reset sdis_n ops as removing prints saying they are DD1 only workaround due to they are permenant steps now 3) add missing content of p9_hcd_core_dcc_skewadjust 4) add DD2 sram_enable support (NOOP for DD1) Change-Id: I74fc3b05781e7cd13bb8c95b0dc7389029d7c5af Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31719 Reviewed-by: Joseph E. Dery <dery@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: CHRISTOPHER M. RIEDL <cmriedl@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31810 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* sector buffer,pulse mode attributesAnusha Reddy Rangareddygari2016-11-081-0/+12
| | | | | | | | | | | | | | | | | | * p9_sbe_chiplet_reset * p9_sbe_npll_setup Change-Id: I488e9cda493e34f36dc60edccd7bec02582878b1 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32106 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32164 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add support for ATTR_PROC_FABRIC_PUMP_MODE in sbe attribute xmlSachin Gupta2016-10-151-2/+8
| | | | | | | | | | Change-Id: I097520e4f05091753ce79d6960e6f94ab27162ba Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31294 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31296 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Lab: DD1 VCS workaround fixYue Du2016-10-141-0/+5
| | | | | | | | | | | | | | | Change-Id: I4830fb203d34d46cfc2f84b24b38a0645fbf30d5 cmvc-coreq:1008525 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31025 Dev-Ready: YUE DU <daviddu@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31029 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* DD2 updates:p9_sbe_arrayinit,p9_sbe_tp_arrayinitAnusha Reddy Rangareddygari2016-10-101-5/+1
| | | | | | | | | | | | | | | | | | | set/reset of dis_n are permanent steps CQ : HW389256 Change-Id: I70022293b7d375f94166a90127c8980038cd08e1 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30872 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Tobias Webel <webel@de.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30876 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* L2 version - p9_sbe_sequence_drtmSantosh2016-10-041-0/+5
| | | | | | | | | | | | | | | Change-Id: Ic1b277304f0ce6057f876be4824626974d32acd0 RTC:156477 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29780 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Abhishek Agarwal <abagarw8@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29818 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* Fixing MC & EP attr_pg for sc model config - p9_sbe_attr.xmlSoma BhanuTej2016-10-031-4/+4
| | | | | | | | | | | | Change-Id: I32cbda6253d63573229dc65a97103158c892b8b5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30455 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30456 Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
* xip_customize: Updated mailbox attribute support.Claus Michael Olsen2016-09-291-147/+117
| | | | | | | | | | | | | | | | | | | | | | | Removed all *_VALID from pervasive_attributes.xml. Removed ATTR_DPLL_FILTER_BYPASS and ATTR_NEST_MEM_X_O_PCIE_FILTER_BYPASS Added ATTR_IS_MPIPL back into p9_sbe_attributes.xml. Initialized ATTR_PG to 0x0000FFFF in sbe_attributes.xml. Added p9_xip_customize_attributes.xml. Change-Id: Idbe457f9e79ca084e91d02b43c6880e9c4279858 CMVC-Prereq: 1006768 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29215 Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29216 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* Unpack attributes for Pervasive targetsSantosh Puranik2016-09-191-1/+39
| | | | | | | | | | | | | | | -- Reserve space for all 64 possible chiplets Change-Id: I21b431205c84c8502b98364eb4c2befc31cdf3d9 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29839 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29840 Reviewed-by: Santosh S. Puranik <santosh.puranik@in.ibm.com>
* Adding in configurations for PNOR/LPC communicationCHRISTINA L. GRAVES2016-09-161-1/+1
| | | | | | | | | | | | | | | | Adjust default LPC base address offset in image (0000030000000000) Change-Id: I98b1ddf8fc9d515b65b20421e9e480ba4def8b9f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28570 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: CHRISTINA L. GRAVES <clgraves@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28571 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* PLL configuration updates -- permit e2e bypass executionJoe McGill2016-09-061-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_sbe_attr_setup p9_setup_sbe_config transmit PLL bypass controls through MBOX Scratch 4 bits 16:20 transmit PLL mux controls through MBOX Scratch 5 bits 12:31 p9_common_poweronoff increase polling delays to account for refclock speed p9_hcd_cache_dpll_setup permit DPLL execution in bypass, based on ATTR_DPLL_BYPASS p9_sbe_npll_setup permit NEST PLL execution in bypass, based on ATTR_NEST_MEM_X_O_PCI_BYPASS p9_mem_pll_setup permit MEM PLL execution in bypass, based on ATTR_NEST_MEM_X_O_PCI_BYPASS p9_sbe_chiplet_pll_setup permit X/O/PCI PLL execution in bypass, based on ATTR_NEST_MEM_X_O_PCI_BYPASS p9_sbe_tp_switch_gears skip adjustment of i2c bit divisor, based on ATTR_NEST_MEM_X_O_PCI_BYPASS p9_sbe_attributes.xml hb_temp_defaults.xml add defaults to enable platform CI Change-Id: Icba6aee79d90b0280ba4818afd92c344c52f52ef Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28611 Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28613 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* SBE move import`Shakeeb2016-09-011-0/+525
Change-Id: I726951318cdb19fd445af2f7910e0d6872eff18c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29086 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
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