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* Account for OMI technology in initial mcs setup for AxoneChristian Geddes2019-08-061-0/+4
| | | | | | | | | | | | | | | | | | | The scom registers that setup the memory channel's intial state get written during the SBE steps. The hwp that does this needs to be updated to account for the changes to the MCFGP0 register that happened between P9N/P9C and P9A. Change-Id: Icfa50177f9fefca3acabbbc41b60f65d280348e7 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81458 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Adam S Hale <adam.samuel.hale@ibm.com> Reviewed-by: Christian R Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81482 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* update i2c bit rate divisor for p9aJoe McGill2019-06-151-0/+5
| | | | | | | | | | | | | | | | | p9a i2cm HW changes require nest/4/2/4 programming Change-Id: Ib29c307fa2250f5096578809e3d0cb10a027086e Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78640 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78664 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* cleanup references to chip-centric EC feature attributesJoe McGill2019-03-221-0/+4
| | | | | | | | | | | | | | | | Change-Id: Ib777b27c6013a647ae86e6ff5973bab19faceb56 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71994 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Reviewed-by: Christopher W. Steffen <cwsteffen@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71999 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* P9: NVDIMM SBE Support to Trigger Catastrophic SaveTsung Yeung2019-01-111-1/+5
| | | | | | | | | | | | | | | | | | | - Adds attribute to indicate which ports contain NVDIMM - Subroutine to trigger CSAVE on ports with NVDIMM Change-Id: I5fc9ead249dda0062ca3ac5237113688a22eb50c CQ:SW452306 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69314 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69817 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Support ATTR_LPC_CONSOLE_CNFG attributeSachin Gupta2018-09-261-0/+4
| | | | | | | | | | | | | | | | | | | | SBE has started supporting LPC console messages on openpower systems. All systems does not support console as its needs LPC/BMC support. So this attribute will be used by SBE to control this feature. HB will customise this attribute in SBE. Change-Id: I7859e53c8f7b7c48ad70f85583026578a05eb448 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66507 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66521 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* nest updates for p9c DD1.3 native and p9c DD1.2 compatibility modesJoe McGill2018-08-291-4/+0
| | | | | | | | | | | | | | | | | | | | | | | HW 446279 - disable update for compat and native modes HW 439321 - disable update for compat, enable for native mode HW 443004 - disable update for compat and native modes HW 446453 - disable update for compat, enable for native mode Change-Id: I3dd1ed6075ff473adbaf342671dd977c53fb2f06 CQ: HW446279 CQ: HW439321 CQ: HW443004 CQ: HW446453 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64067 Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64082 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Updates to permit synchronized SS PLL spreading via TODJoe McGill2018-08-291-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Create EC feature attribute and user override attribute to control application of synchronized spreading. Default to enable synchronized spreading on Axone only. p9_sbe_npll_setup Conditionally skip existing unsynchronized spread enablement p9_tod_init Conditionally invoke spread sync routine after TOD network is running p9_ss_pll_sync Remove from repository, shift code into p9_tod_init to prevent need for mirroring into downstream repositories for FW consumption Change-Id: Ic32c800d58c260136b45fe9561989987d0a97ceb Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63494 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63503 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* SMF: SBE updates for SMF (URMOR set and CPMMR[Runtime Wakeup Mode] clear)Greg Still2018-08-291-0/+4
| | | | | | | | | | | | | | | | | | - set URMOR if MSR[S] bit is set in p9_sbe_load_bootloader - clear CPMMR[Runtime Wakeup Mode] in all cores in p9_sbe_select_ex to ensure Hostboot starts from known state Change-Id: I572a1d9e0ebf8e194c811e2b8c176d145b7361e3 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/61812 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/61817 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Secure memory allocation and setupJenny Huynh2018-07-121-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_mss_eff_grouping.C: - determines whether secure mem is requested, reserves smf space - always reserve smf at end of range because of end-of-range bit - set addr15 when reporting smf base address - mask off group_id(0) via chip address extension if smf is enabled - updated to set value of attr_smf_enabled - enhanced error reporting with smf config/supported values - made values reported to attr_mss_mcs_group_32 more clear p9_mss_setup_bars.C: - set MCFGPA/MCFGPMA registers with SMF data - fixed scom registers for MCFGPA/MCFGPMA hole setup - added note to leave MCFIR_invalid_smf masked for HW451708/HW451711 - added assert to check for HOLE1 and SMF enable overlaps p9_query_mssinfo.C: - updated to print out SMF reservations - print out HTM/OCC/SMF reservations regardless of mirroring enable p9_fbc_utils.C: - prevent group_id(0)=1 from affecting mappable memory ranges p9_sbe_fabricinit.C: - mask off group_id(0) via chip address extension if smf is enabled p9_setup_sbe_config.C, p9_sbe_attr_setup.C: - use scratch_reg6 bit(16) to pass smf_config value initfiles: - removed setup to use other addr bits as secure bit; core only uses addr15 - added setup for ncu addr15 value in hcode - always set addr15 config bit in bridge unit if smf is supported - set addr15 bit across all mcs if smf is enabled - added in settings to enable smf in nmmu unit - hardcode group_id(0) bit in chipext mask for bridge unit if smf is supported attributes: - ATTR_SMF_ENABLE is a system level attribute - changed SMF_ENABLE->SMF_CONFIG; smf_enabled will be (config && supported) CQ:HW451708 CQ:HW451711 Change-Id: I6cf85600354baa322e959c922f596ecc5c68a458 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57322 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Dev-Ready: Brent Wieman <bwieman@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57347 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* set PEC disable store thread based ordering chicken switchesJoe McGill2018-07-101-0/+4
| | | | | | | | | | | | | | | | Change-Id: I2d9aed7833a1bf43c797689d50ff32794ef54cff CQ: SW430383 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62028 Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62042 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_scominit -- unmask TP LFIR bit 37 for CumulusJoe McGill2018-06-081-0/+4
| | | | | | | | | | | | | | | Change-Id: Id216f65d5c240d88c4db62e374c9f3278d623fbb CQ: SW432374 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60118 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60125 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Savory Insomnia -- revert to ordered tlbie mode for CumulusJoe McGill2018-05-031-0/+4
| | | | | | | | | | | | | | | | | | | | | | - configure the fabric & unit snooper logic to operate in ordered/p8 tlbie mode - prohibit the nest mmu from snooping tlbie - adjust NCU tlbie stall settings - revert HW419330 fix on Cumulus only Change-Id: Idf18f81b08c4fb6e372fa4c544c023a8820bb37b CQ: HW440920 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56406 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56415 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add PROC_MEM_TO_USE to SBEspashabk-in2018-04-131-1/+1
| | | | | | | | | | | | | Change-Id: I614bf9b59166dadd84ea5276845f2cd7d897c2cb Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57053 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Elizabeth K. Liner <eliner@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57056
* Abist proc update for SBE changesAbhishek Agarwal2018-04-091-0/+4
| | | | | | | | | | | | | | | Change-Id: I28a11ecc5f64498f495f1575c914c5d3120c6f23 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54243 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56789 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Scommable check before L2/L3 Purge in MPIPL PathRaja Das2018-03-221-0/+7
| | | | | | | | | | | CQ: SW420347 Change-Id: I051b8ff4a0afadb311db24f1c235fdc1a433958f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55838 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Adding attribute to detect which processor we can use for alt-memoryElizabeth Liner2018-03-071-0/+4
| | | | | | | | | | | | | | | | Change-Id: I5e0435c5828dcaddb8571afdbd298c08400cb0e4 RTC:176434 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54585 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54598
* Axone support to TP stopclocksSoma BhanuTej2018-03-021-0/+4
| | | | | | | | | | | | | | | | | | Change-Id: I0960ec588156f3df3f863b6c5fa41bbed95e089e RTC: 183048 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53139 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Dev-Ready: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: NAGENDRA K. GURRAM <nagendra.g@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53152 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Remove workaround for DD1 SW reset for XIVESachin Gupta2018-01-261-4/+0
| | | | | | | | | | | | | | | | Change-Id: Ic2cf3510350aa00c0641cc910824000bf58d8276 RTC: 177741 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52512 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52515 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* MCD disable workaround for HW423589 (option1)Joe McGill2018-01-121-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | chip_ec_attributes.xml add ATTR_CHIP_EC_FEATURE_HW423589_OPTION1, defines set of chips which need MCD disable for HW423589 (applied to Nimbus EC20 and 22+) p9.cxa.scom.initfile p9.int.scom.initfile p9.l2.scan.initfile p9.l3.scan.initfile p9.mmu.scom.initfile p9.ncu.scan.initfile p9.npu.scom.initfile p9.nx.scom.initfile p9.trace.scan.initfile p9.vas.scom.initfile p9_pcie_config.C set unit scope disable dials p9_sbe_scominit.C p9_pm_pba_init.C set PBA unit scope disable dial p9_pm_set_homer_bar.C change PBA0 default command scope from GROUP to NODAL p9.fbc.ab_hp.scom.initfile disable group master setup p9_setup_bars.C p9_setup_bars_defs.H skip MCD setup for HW423589_OPTION1 cmvc-prereq: 1043014 Change-Id: I402701bdd3266e19dbbe8c717b8a54942e3c9ee2 CQ: HW423589 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48961 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48963 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
* disable ECC bypass for Cumulus DD1.0Joe McGill2017-12-191-0/+4
| | | | | | | | | | | | | | | | | | | | | Nimbus DD2.0 disable will go into op910 only (for Boston Coral) but not into master Change-Id: I28376316be3e6700af97df83a02c48e46d715dec CQ: HW415945 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50445 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50453 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* support customized application of filter PLL buckets from AW MVPD keywordJoe McGill2017-12-121-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pervasive_attributes.xml sbe_attributes.xml create ATTR_FILTER_PLL_BUCKET to encapsulate BGoffset selection p9.filter.pll.overlay.scan.initfile generate correct BGoffset value based on ATTR_FILTER_PLL_BUCKET value build must process 4x (ATTR values 1..4) to generate set of ring images p9_xip_customize.C consume AW keyword from MVPD, set ATTR_FILTER_PLL_BUCKET for HB platform and customize into SBE image if attribute is present in image p9_sbe_npll_initf.C p9_sbe_npll_initf_errors.xml re-scan perv_pll_bndy ring with selected BGoffset overlay when ATTR_fILTER_PLL_BUCKET is non-zero p9_sbe_chiplet_pll_initf.C p9_sbe_chiplet_pll_initf_errors.xml adapt to error XML updates in p9_sbe_npll_initf Change-Id: Id09074d12e95ffc44337e32ec683056d8ec390f3 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49442 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com> Reviewed-by: Sumit Kumar <sumit_kumar@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49460 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Adding attribute to turn memory early data onLuke C. Murray2017-12-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Performance wants a way to turn memory early data on & off using just scoms. Adding one attribute to control all the needed scoms and defaulting everything so that early data is off. For the L3 disable cp_me by default using scom Changing the scom cp_me dial to disable cp_me for all systems after Nimbus DD2.0. This is expected to be the correct setup for most systems. We didn't disable the cp_me at the scan, because the scom can only disable cp_me if ON or allow the scan setting if set OFF. Some systems might want cp_me enabled by only changing a scom. So the default is to set cp_me on at the scan and off a the scom. This way only the scom has to be turned off to enable cp_me. Also update three scoms in the memory controler that are needed for early data. Change-Id: Ib2106ec4b7d26cb084601f2d6eee68833b36d30b CQ: HW426419 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49261 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49331 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Chip address extension workaround for HW423589 (option2), part1Joe McGill2017-12-011-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | chip_ec_attributes.xml nest_attributes.xml p9_sbe_attributes.xml add ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE, defines set of chips which physically support the feature add ATTR_CHIP_EC_FEATURE_HW423589_OPTION2, defines set of chips which need extended address workaround for MCD issue (applied only to Nimbus EC 21) add ATTR_MAX_INTERLEAVE_GROUP_SIZE, to restrict maximum size of memory groups formed. Written by p9_mss_eff_grouping. For HW423589_OPTION2, this will default to 512GB add ATTR_FABRIC_ADDR_EXTENSION_[GROUP|CHIP]_ID, to hold extended address configuration. Written by p9_sbe_fabricinit (SBE) and p9_mss_eff_grouping (HB). For HW423589_OPTION2, this will default to 0b0000_111, consuming all chip ID bits for extended addressing. p9_fbc_utils.C p9_fbc_utils.H extend p9_fbc_utils_get_chip_base_address to support address extension, now outputs set of ranges in each msel based on ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID maintain original function for PPE platform which requires knowledge of non-aliased base addresses only, for code size p9_mss_eff_grouping.C p9_mss_eff_grouping_errors.xml set ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID for HB platform restrict size of groups formed for HW423589_OPTION2 p9_sbe_fabricinit.C set ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID for SBE platform configure FBC/NMMU extended addressing registers p9_setup_bars.C p9_setup_bars_defs.H p9_setup_bars_errors.xml add general purpose support for extended address mode for HW423589_OPTION2, configure static MCD setup p9_hcode_image_defines.H p9_hcode_image_build.C customize SGPE image with address extension configuration to apply p9.cxa.scom.initfile p9.int.scom.initfile p9.l2.scom.initfile p9.l3.scom.initfile p9.ncu.scom.initfile p9.nx.scom.initfile p9.trace.scan.initfile p9.vas.scom.initfile p9_hcd_cache_scominit.C p9_hcd_cache_scominit.c p9_pcie_config.C set unit address extension configuration on supported chips p9_rng_init_phase2.C p9_sbe_scominit.C p9c_set_inband_addr.C p9_sbe_load_bootloader.C p9_sbe_mcs_setup.C adapt to alterations in p9_fbc_utils_get_chip_base_address Change-Id: I614d566c073f1169f04f647057e6e85889f1c237 CQ: HW423589 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48576 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48892 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* remove NV iovalid assertion from FW and add scan inits to resolve glsmux xstateJoe McGill2017-11-281-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_sbe_chiplet_reset remove deassertion of OBUS clk async reset, shift to p9_sbe_startclock_chiplets p9_sbe_startclock_chiplets conditionally remove workaround (assert iovalid, clock, deassert iovalid) instituted to flush DL glmux select pipeline, these will be set via scan for supported chips deassert OBUS clk async reset p9_chiplet_scominit remove assertion of NV iovalid from HB p9.npu.scan.initfile alter flush state of NVDL glsmux select pipe latches to 0b10 p9.obus.scan.initfile alter flush state of IOO PHY logic to enable lane clocks clear RX_LANE_ANA_PDWN clear RX_CLKDIST_PDWN set RX_IREF_PDWN_B Change-Id: Ib9d4bf18a181ed1cf55eaf92e1486c494757d657 CQ: HW404391 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50027 Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50029 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Axone UpdateAnusha Reddy Rangareddygari2017-10-241-0/+10
| | | | | | | | | | | | | | | | | * IOF0 pll initf for Axone * Clock mux settings Change-Id: I1c6350bca42fc11e8e2a93f4134ea5db76daf79e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48278 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48282 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Remove HB incorrect setting of ATTR_DD1_SLOW_PCI_REF_CLOCKThi Tran2017-10-041-1/+1
| | | | | | | | | | | | | | | | | Change-Id: I306fbb6ce0a128f61fc58aa4ed10ac53470eeb90 CQ:SW403259 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46988 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47067 Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
* Update p9_sbe_load_bootloader Hwp to receive the addr-key stash-2Raja Das2017-08-111-0/+4
| | | | | | | | | | | | | | | | Change-Id: Id27b43085d1619bc9cfbe854dc46eac6ee85e170 RTC:166124 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35883 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35889 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* Use DD1 SW reset for XIVE unit until we get HW reset working in DD2crgeddes2017-07-311-1/+4
| | | | | | | | | | | | | | | | | | | This is a temporary workaround until we get the HW reset working. Currently we are having issues with the VSD tables not getting cleared correctly when Hostboot tries to initialize interrupts Change-Id: I313cb9cbba63cb0598b663c9792acf798b1c8766 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43632 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43634 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* TP, Nest FIR updates -- DD2 updates to match RAS XMLJoe McGill2017-07-261-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TP Pervasive LFIR - mark bit 21 recoverable to match XML specification - add Nimbus-only workaround for XBUS PLL lock reporting - adjust MEM PLL reset,setup routines to avoid generating spurious attention from MEM PLL FBC IOE TL FIR - mask bits 9,12,15 to match XML specification - mark bits 56..58 checkstop to match XML specification FBC IOO DL FIR - mask bits 56..59, 62..63 to match XML specification - mark bits 60..61 recoverable to match XML specification IO OBUS FIR - mark bit 2 recoverable to match XML specification CXA FIR - update initfile to handle change in number of implemented bits from Nimbus DD1 to DD2 NX CQ FIR - mark bits 6,16,20..21,23..24,28,39 checkstop to match XML specification - mark bit 11 recoverable to match XML specification changes Change-Id: Ic954b2281d1d86ad91e7cd4952923af8c0fa0d8b CQ: HW415692 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42905 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42909 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_tracearray: Nimbus DD2 updatesJoachim Fenkes2017-07-241-0/+4
| | | | | | | | | | | | | | | | | | Adapt "trace still running" check for DD2, and make use of the new "hold trace_run off" functionality in the process. Backwards compatible with DD1. Change-Id: Iab06937700039a5bb9c14acfe4942e4ae1c29352 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41575 Dev-Ready: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41577 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM: Delete deprecated attributesGreg Still2017-07-141-1/+1
| | | | | | | | | | | | | | | | | | | | - Complete the move to platform SYSTEM_*_DISABLED and HWP *_ENABLED attributes - Added VDM DPLL response attribute to CME header mapping - Updated review comments Change-Id: If8f8e42fd94825623315e8a7c28105cca8c8c8b2 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42918 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42919 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Create dmi.pll.scan.initfileBen Gass2017-07-141-0/+4
| | | | | | | | | | | | | | | | | | | | Support sync and async mode for Cumulus MC Default buckets are 1. Change-Id: I62d0221abf7f93030cb8c0200a456609ab4dfe04 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40326 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41056 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* HW414700 checkstop on UEs and disable core ECC counterLuke C. Murray2017-07-131-0/+4
| | | | | | | | | | | | | | | | Core ECP.PC.FIR.THRESHOLD_RESET = 0b00 to disable CXA, L2, L3, NMMU, NX, VAS, FBC, MC FIR changes to checkstop on UE at source Change-Id: I4400acb7d3ec68cced49adb5a77fec7bd8356d40 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42887 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42942 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* mc_pll_bucket attributeAnusha Reddy Rangareddygari2017-07-121-0/+4
| | | | | | | | | | | | | | | | | | | | | | in async mode for Cumulus. Using scratch_reg_2 bits 21:23 shift p9_xip_customize changes to a separate, dependent commit to satisfy HB CI for this commit Change-Id: I44c25c5cfb437298f1102f5275a260b4c5ccf522 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42355 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42356 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* dcc skew adjust procedure updateAnusha Reddy Rangareddygari2017-07-121-0/+9
| | | | | | | | | | | | | | | | | new attributes to support disabling of dccadj and skewadj functionality Change-Id: I4f23b8800a87a3d0d9ce0a0fadfa99e2de03d3f6 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41470 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41472 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Cumulus proc updatesAnusha Reddy Rangareddygari2017-07-121-0/+5
| | | | | | | | | | | | | | | | for osc switch settings Change-Id: I9e762d2c4b552e84a3a2cc48ec0d9d75732b07cf Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41676 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41679 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_select_ex: add fused core booting supportGreg Still2017-07-031-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | - Reads ATTR_FUSED_CORE_MODE attribute in "single" mode. - Checks that the first core found is an even core - Checks that the odd core in the EX associated with the first core is functional - Adds the second core to the CCSR in the OCB for istep 4 use. - Added callouts for Level 3 - Fix error testing bugs - Addressed callout comments - Addressed review comments Change-Id: Id095c1300a96ff52f311836c9dcbe93226014ff0 RTC: 173949 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41149 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41151 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
* L3 update -- p9_suspend_ioThi Tran2017-06-261-1/+4
| | | | | | | | | | | | | | | | | | - Update headers/comments - Added error traces to FAPI_TRY call - Review error FFDC and callout Change-Id: I7b984cf8c6dd9fdd6a55a52a9f95bf6a8461d8c8 RTC:151595 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41301 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41303 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* add support for OBUS PLL bucketsJoe McGill2017-06-231-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_frequency_buckets.H p9.obus.pll.scan.initfile document and support base frequencies 1611 MHz - 25.78G, 156.25 MHz ref 1250 MHz - 25G, 156.25 MHz ref 1200 MHz - 19.2G, 133.33 MHz ref pervasive_attributes.xml define ATTR_OB[0123]_PLL_BUCKET to hold encoded ring bucket select value nest_attributes.xml define ATTR_FREQ_O_MHZ array to hold per chiplet OBUS frequency retain ATTR_FREQ_A_MHZ to serve as FBC A link frequency indicator p9_setup_sbe_config.C p9_sbe_attr_setup.C transmit bucket selection through FSP/BMC->SBE mailbox encode OBUS bucket selects in Scratch Reg2 bits 24:31 p9_sbe_chiplet_pll_initf.C p9_sbe_chiplet_pll_initf_errors.xml scan correct ring image based on bucket selector attributes p9_ringId.C p9_ringId.H p9_ring_id.h accomodate three copies of obX_pll_bndy (use ID previously reserved for obX_pll_func, which should not be necessary to scan init) scan_procedures.mk generateWrapper.pl initCompiler infrastructure changes to support build of bucket data p9.fbc.ab_hp.scom.initfile p9.fbc.ioo_tl.scom.initfile p9_tod_setup.C updates to handle A,O frequency attribute changes CMVC-Prereq: 1027320 CMVC-Prereq: 1027496 CMVC-Prereq: 1027579 Change-Id: I42f9bb4037a587f7e3ec8dd9848bdb853ac3d7a0 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40159 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40164 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Check Scratch Register 3 bit 7 and set new ATTR_SECURE_SETTINGSMike Baiocchi2017-06-071-0/+4
| | | | | | | | | | | | | | | | | | | | Change-Id: Ia125ce6fdf5a15acf30a11e3124fae86c645d96c RTC:163094 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41107 Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Marshall J. Wilks <mjwilks@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41110 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* future proof EC feature attributes, add missing P9N DD2 initsJoe McGill2017-05-311-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | redefine EC feature attributes, using inverse logic where required, to qualify inits specific to P9N DD1 where possible, to eliminate need for updates for future chips in plan attempt to remove usage of generic P9N_DD1_SPY_NAMES and P9N_DD2_SPY_NAMES attributes added to support initial P9NDD2 engineering data -- several spies were not being set as a result ----------------- initfile updates: ----------------- p9.cme.scan.initfile add HW391162, SCAN_SICR_TLBIE_QUIESCE feature attributes p9.core.common.scan.initfile remove fused core init, it was applying scan default for P9N DD1 and is not needed for P9N DD2+ given fuse controls p9.core.scan.initfile add CORE_P9NDD1 to qualify P9N DD1 specific register hierarchy and dial programming replace usage of P9N_DD1_SPY_NAMES, P9N_DD2_SPY_NAMES using CORE_P9NDD1 and inverse, to pick up initial pass at P9C DD1 inits p9.cxa.scom.initfile add CXA_P9NDD1_SPY_NAMES to qualify P9N DD1 specific register hierarchy p9.ddrphy.scom.initfile add DDRPHY_P9NDD1_SPY_NAMES to qualify P9N DD1 specific register hierarchy p9.dpll.scan.initfile remove POSTDD1N_DPLL_SETTINGS feature attribute, use DD1_DPLL_SETTINGS attribute and inverse to drive inits p9.l2.scan.initfile invert definition of OPTIMAL_LARX_STCX_PERF, HW409069 feature attributes p9.l3.scan.initfile p9.l3.scom.initifle remove OPTIMAL_LCO_SCOM, HW396230_SCOM feature attributes use HW386657, HW396230 attributes to drive inits p9.mca.scom.initfile add MCA_P9NDD1_ASYNC to differentiate asynchronous boundary crossing programming and dial name differences between P9N DD1, P9N DD2 p9.mmu.scan.initfile p9.mmu.scom.initfile invert definition of NMMU_DMT_DD2, NMMU_ISS734_DD2_1 feature attributes p9.ncu.scan.initfile p9.ncu.scom.initifle remove HW396230_SCOM, use HW396230 attribute to drive inits p9.npu.scom.initfile remove usage of P9N_DD1_SPY_NAMES, refactor CONFIG_ENABLE_PBUS specification to work for both P9NDD1, P9NDD2 ENGD p9.obus.scan.initfile remove EC qualification of OBUS FIR mask for simulation sample.ec.scan.initfile remove testcase requiring use of P9N_DD1_SPY_NAMES, properties of testcase are covered by other tests ----------------- HWP updates: ----------------- p9_xip_customize add customization of epsilon attributes for NMMU application p9_chiplet_scominit invert definition of P9_NDL_IOVALID feature attribute remove usage of P9N_DD1_SPY_NAMES p9_npu_scominit replace usage of P9N_DD1_SPY_NAMES with SETUP_BARS_NPU_DD1_ADDR p9_sbe_tracearray invert definition of CORE_TRACE_SCOMABLE feature attribute p9_sim_get_nia remove usage of P9N_DD1_SPY_NAMES, directly process CT/EC attributes (ok as this HWP is used for VBU sim only and not consumed by FW) Change-Id: I63bfe8a4bfb8824b94e35a3688a6c69eecc1cf01 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40911 Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40915 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* L3 updates -- p9_build_smp, p9_fbc_utilsJoe McGill2017-05-281-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | p9_build_smp: constrain FFDC collection at 16 chips (current max size for P9 based systems) scrub node references, replace with group clarify X link requirements based on pump mode review and complete callouts p9_fbc_utils: add feature attribute to support pb_init sampling on NDD2+ replace locally defined bit constants with SCOM header file constants Change-Id: Ib1f71488ffd07580a647709d9227112f7d73384f CQ: HW328175 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40308 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: DHRUVARAJ SUBHASH CHANDRAN <dhruvaraj@in.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40310 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_nest_initf -- add HWP support to scan n3_br_fureJoe McGill2017-05-191-0/+5
| | | | | | | | | | | | | | | | | | for chips not affected by HW388874 (Nimbus DD2+), apply scan inits present for n3_br_fure ring Change-Id: Ifa0d17074741478ecdc35d3131c56f6e270a1a79 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39604 Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40114 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* p9_hcd_cache_dcc_skewadjust_setupAnusha Reddy Rangareddygari2017-05-111-0/+9
| | | | | | | | | | | | | | | | DD2 updates Change-Id: Ia58c7ee2d3167289fed83c0f6b8c2da3b2bfb637 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40325 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Michael Koch <michael.koch@de.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40329 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* NMMU Nimbus dd2 scom/scan updates, updated commentsEmmanuel Sacristan2017-05-111-0/+4
| | | | | | | | | | | | | | | | Change-Id: I4b9296793fc8802f03bfebcb46446c8bc1a1d4e3 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39782 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39859 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_attributes.xml -- add entries for effective FBC IDsJoe McGill2017-05-041-0/+8
| | | | | | | | | | | | | | Change-Id: I06860fe44f8fb1436ff78b5041cd1897685694ab Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39922 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39943 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Fix for HW397129-set bit 52 in the ALTD_OPTION reg to keep MC fastpath enabledCHRISTINA L. GRAVES2017-04-061-0/+6
| | | | | | | | | | | | | | | Change-Id: Ifd5be240823ea2ba4fdb6950404b429e33363bd8 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36466 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36468 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_chiplet_reset,p9_sbe_arrayinitAnusha Reddy Rangareddygari2017-03-291-0/+8
| | | | | | | | | | | | | | | | | | | | | * assert SCAN_CLK_USE_EVEN=1 in OPCG_REG1 in cumulus chip MC chiplet * Cumulus only dropping MC chiplet fence during arrayinit Change-Id: Id339b8707cb2caac62068bdea1c93465b43721e2 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38028 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38030 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Attribute support of customization of Nimbus DD1 PCI reference clock speed.Thi Tran2017-03-231-1/+5
| | | | | | | | | | | | | | | Change-Id: I5bb1646868fca15aca744b311ab5d2bc5dd64739 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38297 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38305 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add ec_abst ring to p9n.hw_imageThi Tran2017-03-101-0/+4
| | | | | | | | | | | | | | | Change-Id: Ic6fc899956e0690f75224471917ff904aa03713e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37768 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37773 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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