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path: root/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
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* enable prefetch drop for better MC fairnessShelton Leung2017-09-121-1/+18
* Reducing rng pace rate from 2000 -> 300 for HW403701Jenny Huynh2017-09-121-0/+17
* Updates to run HW VREF cal by defaultStephen Glancy2017-09-121-0/+34
* adjust SRAM timingsJoe McGill2017-09-121-19/+2
* New dummy pulse pok bits (for L2/L3)Alex Taft2017-09-121-0/+34
* NPU scan/scom init updatesRyan Black2017-09-121-0/+17
* Add three WATs, remove IMC2, replace stop2 workaroundNick Klazynski2017-09-121-1/+52
* Add workaround for DDRPHY ODT config register erratum (ODT2, ODT3 bits swapped)Louis Stermole2017-09-121-0/+20
* Workaround to fix issue where Powerbus loses track of EQs in DD1Raja Das2017-09-121-0/+16
* reverting FIRs to master values, setting only bit 8Juan Medina2017-09-121-0/+19
* adding insert for soft fail threshold for dd1 and dd2Joshua Hannan2017-09-121-0/+17
* WAs for HW401811 HW402145 HW403465; DIS_MULTIPLE_TBLW on all modesNick Klazynski2017-09-121-2/+53
* amo cache disabled for dd1 for HW401780Shelton Leung2017-09-121-0/+17
* Adding HW363780 to NPU scom initfilesJenny Huynh2017-09-121-0/+18
* workarounds for HW399919 HW400898 HW398269 HW398269 HW399765Nick Klazynski2017-09-121-0/+137
* Added periodic cal fix - fixes bad delaysStephen Glancy2017-09-121-0/+18
* workaround for hw400932 atag corruptin in prespShelton Leung2017-09-121-0/+17
* dd1 workaround for hw400075 coherency errorShelton Leung2017-09-121-0/+17
* VITAL cleaning for DD2Anusha Reddy Rangareddygari2017-09-121-19/+1
* p9.core.scan.initfile -- mask local error from CC in EC perv LFIRJoe McGill2017-09-121-0/+17
* p9_sbe_tp_chiplet_init3 -- disable TP TOD hang pulseJoe McGill2017-09-121-0/+17
* Updating P9 L2 scan initfile to use attributesLuke Murray2017-09-121-0/+34
* FBC updates for HW383616, HW384245Joe McGill2017-09-121-0/+36
* Adding skip group dials for cache when chip=groupLuke Murray2017-09-121-0/+41
* Adding chip_ec_feature attributes for dd2 buildBen Gass2017-09-121-0/+1312
* add SS PLL settings to support 94 MHz PCI operationJoe McGill2017-09-121-0/+18
* p9_getecid -- set PCIE DD1.0x workaround attributesJoe McGill2017-09-121-0/+34
* Add MSS customization support from CRP0 Lx MVPDJoe McGill2017-09-121-35/+1
* Security control override disable support - p9_setup_sbe_configSoma BhanuTej2017-09-121-18/+0
* p9.fbc.scan.initfile -- clock off MCSYNC staging latchesJoe McGill2017-09-121-0/+18
* HW396520: DD1 workaround skip flushmode inhibit drop in cache hwpYue Du2017-09-121-0/+17
* Add Memory Subsystem FIR supportBrian Silver2017-09-121-0/+17
* Adding in defect HW395947,HW930007 to INT initfilesJenny Huynh2017-09-121-1/+72
* Add EC workaround for PHY training bad bit processingBrian Silver2017-09-121-1/+20
* scan inits for lab workaround for DI bug HW392781Shelton Leung2017-09-121-0/+17
* p9_sbe_lpc_init fix with GPIO resetCHRISTINA L. GRAVES2017-09-121-0/+16
* Adding workaround for HW930007 and HW386013Jenny Huynh2017-09-121-0/+18
* Istep4: Enable poll for DPLL lock in p9_hcd_cache_dpll_setupYue Du2017-09-121-0/+18
* Add EC feature levels to MSS workaroundsBrian Silver2017-09-121-12/+140
* p9_psi_init -- parametrize link speed (half/full)Joe McGill2017-09-121-0/+18
* PPM reg collision (HW389511) work-around: Special Wake-upChristopher Riedl2017-09-121-0/+17
* p9.fbc.scan.initfile -- create initfile, add workaround for HW376651Joe McGill2017-09-121-0/+18
* HW388878 VCS workaroundJoe McGill2017-09-121-3/+3
* Cache HWP: DD1 VCS WorkaroundYue Du2017-09-121-0/+18
* Change chip to unsecure always for DD1 chipsSoma BhanuTej2017-09-121-0/+18
* DD2 updates:p9_sbe_arrayinit,p9_sbe_tp_arrayinitAnusha Reddy Rangareddygari2017-09-121-19/+1
* Procedures modified for DD1 changesSunil.Kumar2017-09-121-0/+17
* Ec_level attribute support for DD1 attributesAnusha Reddy Rangareddygari2017-09-121-0/+73
* Add p9_proc_gettracearray procedureJoachim Fenkes2017-09-121-1/+19
* Procedure crashes when trying to query an EC featureRichard J. Knight2017-09-121-0/+76
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