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| author | Joe McGill <jmcgill@us.ibm.com> | 2016-10-19 11:54:47 -0500 |
|---|---|---|
| committer | spashabk-in <shakeebbk@in.ibm.com> | 2017-09-12 00:12:11 -0500 |
| commit | 894b68c8910bd0ab299bb063f819a4291a4acb57 (patch) | |
| tree | 63e943141edd6bd30d113edd80198eea29b655c6 /src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | |
| parent | 920c88b5d6f187a64eee9e07cd7bad9e3dc919a9 (diff) | |
| download | talos-sbe-894b68c8910bd0ab299bb063f819a4291a4acb57.tar.gz talos-sbe-894b68c8910bd0ab299bb063f819a4291a4acb57.zip | |
p9_psi_init -- parametrize link speed (half/full)
Wrapper tested on zzfp033
Appears to correctly trigger half speed mode from FSP tool feedback
$ cat /sys/devices/psi_link0/clock
FSP-2, PSI(0) CLK overwrite: 1 Speed: 166 MHz
Change-Id: I9002d3e6cfc018108cfe342964267372cb461827
Original-Change-Id: I45997c30e71457ceedfcba70550f0e6d98584a1e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31497
Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index b686742f..e73f28fc 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -234,4 +234,22 @@ </chipEcFeature> </attribute> <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_PSI_HALF_SPEED</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Nimbus DD1 only: enable half speed PSI link operation due to relaxed + chip timing closure + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> </attributes> |
