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| author | Brian Silver <bsilver@us.ibm.com> | 2016-12-06 10:09:14 -0600 |
|---|---|---|
| committer | spashabk-in <shakeebbk@in.ibm.com> | 2017-09-12 00:12:23 -0500 |
| commit | 1835b8d95b2ddd3235df80fe0f457e49e20f395d (patch) | |
| tree | 16003ee0ede473e5134253fcdcd468ae92f6f2fc /src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | |
| parent | 6f0f203057e988056db39f3b4d9d8ef16b3e2403 (diff) | |
| download | talos-sbe-1835b8d95b2ddd3235df80fe0f457e49e20f395d.tar.gz talos-sbe-1835b8d95b2ddd3235df80fe0f457e49e20f395d.zip | |
Add EC workaround for PHY training bad bit processing
Change-Id: I1506878ec0951335f62dacb24011806413d74f08
Original-Change-Id: Ia23b7bb80ae0875c869104b0557e7758d4df80a5
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33465
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Dev-Ready: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 50b06e3d..15020faf 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -199,7 +199,7 @@ </chip> </chipEcFeature> </attribute> - <!-- ******************************************************************** --> + <!-- ******************************************************************** --> <attribute> <id>ATTR_CHIP_EC_FEATURE_HW388878</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -446,6 +446,25 @@ </chipEcFeature> </attribute> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_MSS_TRAINING_BAD_BITS</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + For Nimbus pre DD1.02 we want to pass DDR training if we see 'correctable' + errors. This isn't the case for post-DD1.02 where we want to pass/fail + training based on the results from the PHY itself + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> <!-- End Memory Section --> <!-- ******************************************************************** --> |
