treewide: use print function instead of statement

This enables better compat between python2.7 and python3.x

Without this change, building with python3.x (python3.5 tested) as
/usr/bin/python will result in the following error:

File: "sbe/src/build/security/securityRegListGen.py", line 64
    -v, --verbose            enable verbose traces"
                                                  ^
SyntaxError: Missing parentheses in call to 'print'

Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>

Change-Id: Id617f54096fca5cc5fcd829767595a85350e343d
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/89618
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>

56 files changed, 271 insertions, 224 deletions

diff --git a/src/test/testcases/testAbort.py b/src/test/testcases/testAbort.py
index eeaceb9c..33314443 100755
--- a/src/test/testcases/testAbort.py
+++ b/src/test/testcases/testAbort.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
@@ -65,4 +66,4 @@ else:
         #sys.exit(1)
     else:
         print ("\nTest Suite completed with no errors")
-        #sys.exit(0);
\ No newline at end of file
+        #sys.exit(0);
diff --git a/src/test/testcases/testAduMem_124B.py b/src/test/testcases/testAduMem_124B.py
index 91a193c5..8e0804ed 100644
--- a/src/test/testcases/testAduMem_124B.py
+++ b/src/test/testcases/testAduMem_124B.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 import os
 import struct
@@ -51,8 +52,8 @@ def main( ):
             if(data == readData):
                 print ("Success - Write-Read ADU byte["+str(byte)+"] offset[" + str(offset)+"]")
             else:
-                print [hex(a) for a in data]
-                print [hex(a) for a in readData]
+                print([hex(a) for a in data])
+                print([hex(a) for a in readData])
                 raise Exception('data mistmach')
 
 # Test case 2: Invalid length - 3
diff --git a/src/test/testcases/testAduMem_ecc.py b/src/test/testcases/testAduMem_ecc.py
index c427bc9a..d85e0e7c 100644
--- a/src/test/testcases/testAduMem_ecc.py
+++ b/src/test/testcases/testAduMem_ecc.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
@@ -45,8 +46,8 @@ def main( ):
     if(data == readData):
         print ("Success - Write-Read ADU with ECC")
     else:
-        print data
-        print readData
+        print(data)
+        print(readData)
         raise Exception('data mistmach')
 
     # Partial Write test
@@ -60,10 +61,10 @@ def main( ):
     if(sandwichData == readBackData):
         print ("Success - Write_Part-Read ADU with ECC")
     else:
-        print readData
-        print data
-        print readBackData
-        print sandwichData
+        print(readData)
+        print(data)
+        print(readBackData)
+        print(sandwichData)
         raise Exception('data mistmach')
 
 #-------------------------------------------------
diff --git a/src/test/testcases/testAduMem_itag.py b/src/test/testcases/testAduMem_itag.py
index 1172ef94..9ea72572 100644
--- a/src/test/testcases/testAduMem_itag.py
+++ b/src/test/testcases/testAduMem_itag.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
@@ -57,8 +58,8 @@ def main( ):
     if(data == readData):
         print ("Success - Write-Read ADU with Itag")
     else:
-        print data
-        print readData
+        print(data)
+        print(readData)
         raise Exception('data mistmach')
 
     # Partial Write test
@@ -72,10 +73,10 @@ def main( ):
     if(sandwichData == readBackData):
         print ("Success - Write_Part-Read ADU with Itag")
     else:
-        print readData
-        print data
-        print readBackData
-        print sandwichData
+        print(readData)
+        print(data)
+        print(readBackData)
+        print(sandwichData)
         raise Exception('data mistmach')
 #-------------------------------------------------
 # Calling all test code
diff --git a/src/test/testcases/testAduMem_noEccNoItag.py b/src/test/testcases/testAduMem_noEccNoItag.py
index b4350561..a899ca1d 100644
--- a/src/test/testcases/testAduMem_noEccNoItag.py
+++ b/src/test/testcases/testAduMem_noEccNoItag.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 import os
 import struct
@@ -58,8 +59,8 @@ def main( ):
     if(data == readData):
         print ("Success - Write-Read ADU")
     else:
-        print data
-        print readData
+        print(data)
+        print(readData)
         raise Exception('data mistmach')
 
     # Partial Write test
@@ -72,10 +73,10 @@ def main( ):
     if(sandwichData == readBackData):
         print ("Success - Write_Part-Read ADU")
     else:
-        print readData
-        print data
-        print readBackData
-        print sandwichData
+        print(readData)
+        print(data)
+        print(readBackData)
+        print(sandwichData)
         raise Exception('data mistmach')
 
 
diff --git a/src/test/testcases/testAduMem_withEccItag.py b/src/test/testcases/testAduMem_withEccItag.py
index 27740483..53b34042 100644
--- a/src/test/testcases/testAduMem_withEccItag.py
+++ b/src/test/testcases/testAduMem_withEccItag.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
@@ -45,8 +46,8 @@ def main( ):
     if(data == readData):
         print ("Success - Write-Read ADU with ECC,Itag")
     else:
-        print data
-        print readData
+        print(data)
+        print(readData)
         raise Exception('data mistmach')
 
     # Partial Write test
@@ -60,10 +61,10 @@ def main( ):
     if(sandwichData == readBackData):
         print ("Success - Write_Part-Read ADU with ECC,Itag")
     else:
-        print readData
-        print data
-        print readBackData
-        print sandwichData
+        print(readData)
+        print(data)
+        print(readBackData)
+        print(sandwichData)
         raise Exception('data mistmach')
 #-------------------------------------------------
 # Calling all test code
diff --git a/src/test/testcases/testAduMem_withEccWithItagReadWrite.py b/src/test/testcases/testAduMem_withEccWithItagReadWrite.py
index c821cf2b..dcb20caf 100644
--- a/src/test/testcases/testAduMem_withEccWithItagReadWrite.py
+++ b/src/test/testcases/testAduMem_withEccWithItagReadWrite.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
diff --git a/src/test/testcases/testCntlInstruction.py b/src/test/testcases/testCntlInstruction.py
index 1ac0cf4b..26ba7500 100644
--- a/src/test/testcases/testCntlInstruction.py
+++ b/src/test/testcases/testCntlInstruction.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
diff --git a/src/test/testcases/testContinueMpipl.py b/src/test/testcases/testContinueMpipl.py
index 3257811e..7f7cd850 100755
--- a/src/test/testcases/testContinueMpipl.py
+++ b/src/test/testcases/testContinueMpipl.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
diff --git a/src/test/testcases/testContinueSbeBoot.py b/src/test/testcases/testContinueSbeBoot.py
index 84de959b..4586fc36 100755
--- a/src/test/testcases/testContinueSbeBoot.py
+++ b/src/test/testcases/testContinueSbeBoot.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
diff --git a/src/test/testcases/testEnterMpipl.py b/src/test/testcases/testEnterMpipl.py
index f5598887..8545e212 100755
--- a/src/test/testcases/testEnterMpipl.py
+++ b/src/test/testcases/testEnterMpipl.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
diff --git a/src/test/testcases/testExecutorCntrlTimer.py b/src/test/testcases/testExecutorCntrlTimer.py
index 96e6809d..e065c781 100644
--- a/src/test/testcases/testExecutorCntrlTimer.py
+++ b/src/test/testcases/testExecutorCntrlTimer.py
@@ -23,6 +23,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import testPSUUtil
 import testRegistry as reg
 import testUtil
@@ -100,12 +101,12 @@ def main():
     # Intialize the class obj instances
     regObj = testPSUUtil.registry() # Registry obj def for operation
 
-    print "\n  Execute SBE Test set1  [ PutCntrlTimer ] ...\n"
+    print("\n  Execute SBE Test set1  [ PutCntrlTimer ] ...\n")
 
     '''
     Test Case 1
     '''
-    print "\n  Test Start timer\n"
+    print("\n  Test Start timer\n")
     # HOST->SBE data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_startTimer )
 
@@ -116,13 +117,13 @@ def main():
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, host_test_Timer_Cmd_success )
 
     #Poll on HOST DoorBell Register for interrupt
-    print "\n  Poll on Host side for Timer INTR  ...\n"
+    print("\n  Poll on Host side for Timer INTR  ...\n")
     regObj.pollingOn( testPSUUtil.simSbeObj, timer_polling_data, 50 )
 
     '''
     Test Case 2. Stop timer when timer already expired
     '''
-    print "\n  Test Stop timer\n"
+    print("\n  Test Stop timer\n")
     # HOST->SBE data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_StopTimer )
 
diff --git a/src/test/testcases/testExecutorMemory.py b/src/test/testcases/testExecutorMemory.py
index aec0375e..fb738738 100644
--- a/src/test/testcases/testExecutorMemory.py
+++ b/src/test/testcases/testExecutorMemory.py
@@ -36,7 +36,7 @@
 #      1.0     gkeishin     29/03/16     Initial create
 #############################################################
 '''
-
+from __future__ import print_function
 import testClass as testObj
 import testRegistry as reg
 sys.path.append("targets/p9_nimbus/sbeTest" )
@@ -67,17 +67,17 @@ sbe_test_data = (
 def main():
 
     # Intialize the class obj instances
-    print "\n  Initializing Registry instances ...."
+    print("\n  Initializing Registry instances ....")
     regObj = testObj.registry() # Registry obj def for operation
 
-    print "\n  Execute SBE Test set  [ Indirect Commands ] ...\n"
+    print("\n  Execute SBE Test set  [ Indirect Commands ] ...\n")
                                    # Sim obj Target    Test set 
     rc_test = regObj.ExecuteTestOp(testObj.simMemObj,sbe_test_data)
     if rc_test != testObj.SUCCESS:
-        print "  SBE Test data set .. [ FAILED ] .."
+        print("  SBE Test data set .. [ FAILED ] ..")
     else:
-        print "  SBE Test data set .. [ SUCCESS ] "
-    print "\n"
+        print("  SBE Test data set .. [ SUCCESS ] ")
+    print("\n")
 
 if __name__=="__main__":
     if testUtil.getMachineName() == "axone":
diff --git a/src/test/testcases/testExecutorPSU.py b/src/test/testcases/testExecutorPSU.py
index c01287b4..cac232af 100644
--- a/src/test/testcases/testExecutorPSU.py
+++ b/src/test/testcases/testExecutorPSU.py
@@ -36,7 +36,7 @@
 #      1.0     gkeishin     29/03/16     Initial create
 #############################################################
 '''
-
+from __future__ import print_function
 import testPSUUtil
 import testRegistry as reg
 sys.path.append("targets/p9_nimbus/sbeTest" )
@@ -119,25 +119,25 @@ sample_test_data = (
 def main():
 
     # Intialize the class obj instances
-    print "\n  Initializing Registry instances ...."
+    print("\n  Initializing Registry instances ....")
     regObj = testPSUUtil.registry() # Registry obj def for operation
 
-    print "\n  Execute SBE Test set  [ PSU ] ...\n"
+    print("\n  Execute SBE Test set  [ PSU ] ...\n")
                                    # Sim obj Target    Test set     Raise Exception
     rc_test = regObj.ExecuteTestOp(testPSUUtil.simSbeObj,sbe_test_data, True)
     if rc_test != testPSUUtil.SUCCESS:
-        print "  SBE Test data set .. [ Failed ] .."
+        print("  SBE Test data set .. [ Failed ] ..")
     else:
-        print "  SBE Test data set .. [ OK ] "
-        print "\n  Poll on Host side for INTR  ...\n"
+        print("  SBE Test data set .. [ OK ] ")
+        print("\n  Poll on Host side for INTR  ...\n")
                                    # Sim obj Target    Test set     Max timedout
         rc_intr = regObj.pollingOn(testPSUUtil.simSbeObj,host_test_data,20)
         if rc_intr == testPSUUtil.SUCCESS:
-            print "  Interrupt Event Recieved .. Success !!"
+            print("  Interrupt Event Recieved .. Success !!")
         else:
-            print "  Interrupt not Recieved.. Exiting .."
+            print("  Interrupt not Recieved.. Exiting ..")
 
-    print "\n"
+    print("\n")
 
 if __name__=="__main__":
     if testUtil.getMachineName() == "axone":
diff --git a/src/test/testcases/testExecutorPutRing.py b/src/test/testcases/testExecutorPutRing.py
index 4585d7f5..9d3ea802 100644
--- a/src/test/testcases/testExecutorPutRing.py
+++ b/src/test/testcases/testExecutorPutRing.py
@@ -143,7 +143,7 @@ def main():
     # Intialize the class obj instances
     regObj = testPSUUtil.registry() # Registry obj def for operation
 
-    print "\n  Execute SBE Test set1  [ Put Ring ] ...\n"
+    print("\n  Execute SBE Test set1  [ Put Ring ] ...\n")
 
     '''
     Test Case 1
@@ -151,7 +151,7 @@ def main():
     # HOST->SBE data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data1 )
 
-    print "\n  Poll on Host side for INTR  ...\n"
+    print("\n  Poll on Host side for INTR  ...\n")
     #Poll on HOST DoorBell Register for interrupt
     regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 )
 
@@ -160,56 +160,56 @@ def main():
 
 #   Commenting out test cases for perv and proc chiplets, as there is no
 #   way to stop cloks for these chiplets from the test framework
-#    print "\n  Execute SBE Test set2  [ Put Ring ] ...\n"
+#    print("\n  Execute SBE Test set2  [ Put Ring ] ...\n")
 #    '''
 #    Test Case 2
 #    '''
 #    # HOST->SBE data set execution
 #    regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data2 )
 #
-#    print "\n  Poll on Host side for INTR  ...\n"
+#    print("\n  Poll on Host side for INTR  ...\n")
 #    #Poll on HOST DoorBell Register for interrupt
 #    regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 )
 #
 #    #SBE->HOST data set execution
 #    regObj.ExecuteTestOp( testPSUUtil.simSbeObj, host_test_data_success )
 #
-#    print "\n  Execute SBE Test set3 [ Put Ring ] ...\n"
+#    print("\n  Execute SBE Test set3 [ Put Ring ] ...\n")
 #    '''
 #    Test Case 3
 #    '''
 #    # HOST->SBE data set execution
 #    regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data3 )
 #
-#    print "\n  Poll on Host side for INTR  ...\n"
+#    print("\n  Poll on Host side for INTR  ...\n")
 #    #Poll on HOST DoorBell Register for interrupt
 #    regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 )
 #
 #    #SBE->HOST data set execution
 #    regObj.ExecuteTestOp( testPSUUtil.simSbeObj, host_test_data_success )
 #
-    print "\n  Execute SBE Test set4  [ Put Ring ] ...\n"
+    print("\n  Execute SBE Test set4  [ Put Ring ] ...\n")
     '''
     Test Case 4
     '''
     # HOST->SBE data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data4 )
 
-    print "\n  Poll on Host side for INTR  ...\n"
+    print("\n  Poll on Host side for INTR  ...\n")
     #Poll on HOST DoorBell Register for interrupt
     regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 )
 
     #SBE->HOST data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, host_test_data_success )
 
-    print "\n  Execute SBE Test set5  [ Put Ring ] ...\n"
+    print("\n  Execute SBE Test set5  [ Put Ring ] ...\n")
     '''
     Test Case 5
     '''
     # HOST->SBE data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data5 )
 
-    print "\n  Poll on Host side for INTR  ...\n"
+    print("\n  Poll on Host side for INTR  ...\n")
     #Poll on HOST DoorBell Register for interrupt
     regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 )
 
diff --git a/src/test/testcases/testExecutorStopTimer.py b/src/test/testcases/testExecutorStopTimer.py
index 1cc62053..8b98d8b9 100644
--- a/src/test/testcases/testExecutorStopTimer.py
+++ b/src/test/testcases/testExecutorStopTimer.py
@@ -23,6 +23,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import testPSUUtil
 import testRegistry as reg
 import testUtil
@@ -98,12 +99,12 @@ def main():
     # Intialize the class obj instances
     regObj = testPSUUtil.registry() # Registry obj def for operation
 
-    print "\n  Execute SBE Test set1  [ PutCntrlTimer ] ...\n"
+    print("\n  Execute SBE Test set1  [ PutCntrlTimer ] ...\n")
 
     '''
     Test Case 1
     '''
-    print "\n  Test Start timer\n"
+    print("\n  Test Start timer\n")
     # HOST->SBE data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_startTimer )
 
@@ -113,7 +114,7 @@ def main():
     #SBE->HOST data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, host_test_Timer_Cmd_success )
 
-    print "\n  Test Stop timer\n"
+    print("\n  Test Stop timer\n")
     # HOST->SBE data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_StopTimer )
 
@@ -126,13 +127,13 @@ def main():
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, host_test_Timer_Cmd_success )
     try:
         #Poll on HOST DoorBell Register for interrupt
-        print "\n  Poll on Host side for Timer INTR  ...\n"
+        print("\n  Poll on Host side for Timer INTR  ...\n")
         regObj.pollingOn( testPSUUtil.simSbeObj, timer_polling_data, 20 )
     except:
         isTimerFired = False
 
     if isTimerFired:
-        print "\n  Problem. Timer not cancelled\n"
+        print("\n  Problem. Timer not cancelled\n")
         raise Exception('Timer Not cancelled ');
 
 if __name__ == "__main__":
diff --git a/src/test/testcases/testFastArray.py b/src/test/testcases/testFastArray.py
index dbba1baa..bee60693 100644
--- a/src/test/testcases/testFastArray.py
+++ b/src/test/testcases/testFastArray.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
diff --git a/src/test/testcases/testFifoReset.py b/src/test/testcases/testFifoReset.py
index 28c99287..ba5a271c 100644
--- a/src/test/testcases/testFifoReset.py
+++ b/src/test/testcases/testFifoReset.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest")
 sys.path.append("targets/p9_axone/sbeTest" )
diff --git a/src/test/testcases/testFlushNVDIMM.py b/src/test/testcases/testFlushNVDIMM.py
index a7d6ca17..e2983db6 100755
--- a/src/test/testcases/testFlushNVDIMM.py
+++ b/src/test/testcases/testFlushNVDIMM.py
@@ -22,7 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
-
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
diff --git a/src/test/testcases/testGetCapabilities.py b/src/test/testcases/testGetCapabilities.py
index f6aedcec..ed451cfa 100755
--- a/src/test/testcases/testGetCapabilities.py
+++ b/src/test/testcases/testGetCapabilities.py
@@ -5,7 +5,7 @@
 #
 # OpenPOWER sbe Project
 #
-# Contributors Listed Below - COPYRIGHT 2015,2019
+# Contributors Listed Below - COPYRIGHT 2015,2020
 # [+] International Business Machines Corp.
 #
 #
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
@@ -62,6 +63,9 @@ EXPDATA3 = [0xa8,0x0,0x0,0x03, #getcapability/getSbeFFDC/quiesce
 #-------------------------------------------------
 def main( ):
     ( rc, out )  =   quiet_run_command( "sbe-ddlevel 0", output_modes.regular )
+    if(rc == "DD1"):
+        print("Not running Get Capabilities on DD1")
+        return
     testUtil.runCycles( 10000000 )
     testUtil.writeUsFifo( TESTDATA )
     testUtil.writeEot( )
diff --git a/src/test/testcases/testGetMem.py b/src/test/testcases/testGetMem.py
index 535a10f4..3d929a58 100644
--- a/src/test/testcases/testGetMem.py
+++ b/src/test/testcases/testGetMem.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
diff --git a/src/test/testcases/testGetMem_expdata.py b/src/test/testcases/testGetMem_expdata.py
index f0c5214a..fa7ef4c6 100644
--- a/src/test/testcases/testGetMem_expdata.py
+++ b/src/test/testcases/testGetMem_expdata.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
diff --git a/src/test/testcases/testGetRing.py b/src/test/testcases/testGetRing.py
index ca8da56d..a1ade679 100644
--- a/src/test/testcases/testGetRing.py
+++ b/src/test/testcases/testGetRing.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
diff --git a/src/test/testcases/testHostFFDC.py b/src/test/testcases/testHostFFDC.py
index af5ec676..cb107b7b 100644
--- a/src/test/testcases/testHostFFDC.py
+++ b/src/test/testcases/testHostFFDC.py
@@ -22,7 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
-
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
@@ -117,12 +117,12 @@ def main():
     # Intialize the class obj instances
     regObj = testPSUUtil.registry() # Registry obj def for operation
 
-    print "\n  Execute SBE Test - Set FFDC Address\n"
+    print("\n  Execute SBE Test - Set FFDC Address\n")
 
     # HOST->SBE data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data )
 
-    print "\n  Poll on Host side for INTR  ...\n"
+    print("\n  Poll on Host side for INTR  ...\n")
     #Poll on HOST DoorBell Register for interrupt
     regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 )
 
@@ -135,7 +135,7 @@ def main():
     # HOST->SBE data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_invalid_ring )
 
-    print "\n  Poll on Host side for INTR  ...\n"
+    print("\n  Poll on Host side for INTR  ...\n")
     #Poll on HOST DoorBell Register for interrupt
     regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 )
 
diff --git a/src/test/testcases/testIstepAuto.py b/src/test/testcases/testIstepAuto.py
index d68d2135..28c0551f 100755
--- a/src/test/testcases/testIstepAuto.py
+++ b/src/test/testcases/testIstepAuto.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 import copy
 from sim_commands import *
@@ -103,7 +104,7 @@ def sbe_istep_func( inum1, inum2, node=0, isfleetwood=0):
         lIstepArray[startMajor][1] = lIstepArray[startMajor][0]
     for major in range(startMajor, endMajor+1):
         for minor in range(lIstepArray[major][0], lIstepArray[major][1] + 1):
-            print "Running:"+str(major)+"."+str(minor)
+            print("Running:"+str(major)+"."+str(minor))
 
             try:
                 TESTDATA = [0,0,0,3,
diff --git a/src/test/testcases/testIstepInvalid.py b/src/test/testcases/testIstepInvalid.py
index 3123ee03..95068d68 100755
--- a/src/test/testcases/testIstepInvalid.py
+++ b/src/test/testcases/testIstepInvalid.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
diff --git a/src/test/testcases/testIstepInvalidFenced.py b/src/test/testcases/testIstepInvalidFenced.py
index b5c0b795..67cdca13 100755
--- a/src/test/testcases/testIstepInvalidFenced.py
+++ b/src/test/testcases/testIstepInvalidFenced.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
diff --git a/src/test/testcases/testIstepSuccess.py b/src/test/testcases/testIstepSuccess.py
index 28ffccab..f88cd708 100755
--- a/src/test/testcases/testIstepSuccess.py
+++ b/src/test/testcases/testIstepSuccess.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
diff --git a/src/test/testcases/testMatchStashPair.py b/src/test/testcases/testMatchStashPair.py
index d8c0f686..fc683828 100644
--- a/src/test/testcases/testMatchStashPair.py
+++ b/src/test/testcases/testMatchStashPair.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
@@ -49,8 +50,8 @@ def main( ):
     if(data == readData):
         print ("Success - Write-Read PBA - WO FMODE, WO LCO")
     else:
-        print data
-        print readData
+        print(data)
+        print(readData)
         raise Exception('data mistmach')
 #-------------------------------------------------
 # Calling all test code
diff --git a/src/test/testcases/testMemPBA.py b/src/test/testcases/testMemPBA.py
index e57bb6df..ab3db87e 100644
--- a/src/test/testcases/testMemPBA.py
+++ b/src/test/testcases/testMemPBA.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
@@ -43,8 +44,8 @@ def main( ):
     if(data == readData):
         print ("Success - Write-Read PBA - WO FMODE, WO LCO")
     else:
-        print data
-        print readData
+        print(data)
+        print(readData)
         raise Exception('data mistmach')
     # Partial Write test
     readData = testMemUtil.getmem(0x08000000, 128*3, 0x02)
@@ -56,10 +57,10 @@ def main( ):
     if(sandwichData == readBackData):
         print ("Success - Write_Part-Read PBA - WO FMODE, WO LCO")
     else:
-        print readData
-        print data
-        print readBackData
-        print sandwichData
+        print(readData)
+        print(data)
+        print(readBackData)
+        print(sandwichData)
         raise Exception('data mistmach')
 
 # Second Case with Fast Mode without LCO
@@ -73,8 +74,8 @@ def main( ):
     if(data == readData):
         print ("Success - Write-Read PBA - W FMODE, WO LCO")
     else:
-        print data
-        print readData
+        print(data)
+        print(readData)
         raise Exception('data mistmach')
     # Partial Write test
     readData = testMemUtil.getmem(0x08000000, 128*3, 0x22)
@@ -86,10 +87,10 @@ def main( ):
     if(sandwichData == readBackData):
         print ("Success - Write_Part-Read PBA - W FMODE, WO LCO")
     else:
-        print readData
-        print data
-        print readBackData
-        print sandwichData
+        print(readData)
+        print(data)
+        print(readBackData)
+        print(sandwichData)
         raise Exception('data mistmach')
 
 # Third Case with Fast Mode with LCO
@@ -103,8 +104,8 @@ def main( ):
     if(data == readData):
         print ("Success - Write-Read PBA - W FMODE, W LCO")
     else:
-        print data
-        print readData
+        print(data)
+        print(readData)
         raise Exception('data mistmach')
     # Partial Write test
     readData = testMemUtil.getmem(0x08000000, 128*3, 0x62)
@@ -116,10 +117,10 @@ def main( ):
     if(sandwichData == readBackData):
         print ("Success - Write_Part-Read PBA - W FMODE, W LCO")
     else:
-        print readData
-        print data
-        print readBackData
-        print sandwichData
+        print(readData)
+        print(data)
+        print(readBackData)
+        print(sandwichData)
         raise Exception('data mistmach')
 
 #-------------------------------------------------
diff --git a/src/test/testcases/testMemUtil.py b/src/test/testcases/testMemUtil.py
index b7d02c2d..7ae48569 100644
--- a/src/test/testcases/testMemUtil.py
+++ b/src/test/testcases/testMemUtil.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 import os
 import struct
@@ -141,8 +142,8 @@ def getmem(addr, len, flags):
 
     readLen = testUtil.readDsEntryReturnVal()
     if(getsingleword(lenExp) != list(readLen)):
-        print getsingleword(lenExp)
-        print list(readLen)
+        print(getsingleword(lenExp))
+        print(list(readLen))
         raise Exception("Invalid Length")
 
     expResp =  [0xc0,0xde,0xa4,0x01,
@@ -185,7 +186,7 @@ def setUnsecureMemRegion(addr, size, controlFlag, responseWord):
     # Host to SBE req
     regObj = testPSUUtil.registry()
     regObj.ExecuteTestOp(testPSUUtil.simSbeObj, req)
-    print "\n  Poll on Host side for INTR  ...\n"
+    print("\n  Poll on Host side for INTR  ...\n")
     #Poll on HOST DoorBell Register for interrupt
     regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5)
 
diff --git a/src/test/testcases/testPSUGetCapabilities.py b/src/test/testcases/testPSUGetCapabilities.py
index 456ae306..07eea3d4 100644
--- a/src/test/testcases/testPSUGetCapabilities.py
+++ b/src/test/testcases/testPSUGetCapabilities.py
@@ -22,7 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
-
+from __future__ import print_function
 import sys
 import os
 import struct
@@ -114,7 +114,7 @@ def getCapabilities(addr, size, exp_status):
     )
     # HOST->SBE data set execution - Less length setup
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data )
-    print "\n  Poll on Host side for INTR  ...\n"
+    print("\n  Poll on Host side for INTR  ...\n")
     #Poll on HOST DoorBell Register for interrupt
     regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 )
     #SBE->HOST data set execution
@@ -127,12 +127,12 @@ def main():
     # Run Simics initially
     testUtil.runCycles( 100000000 )
 
-    print "\n  Execute SBE Test - negative testcase - less size\n"
+    print("\n  Execute SBE Test - negative testcase - less size\n")
     getCapabilities(0x08000000, 30, 0x00020019)
-    print "\n  Execute SBE Test - negative testcase - not multiple of PBA\n"
+    print("\n  Execute SBE Test - negative testcase - not multiple of PBA\n")
     getCapabilities(0x08000000, 129, 0x00020019)
 
-    print "\n  Execute SBE Test - positive testcase \n"
+    print("\n  Execute SBE Test - positive testcase \n")
     getCapabilities(0x08000000, 128, 0)
 
     testUtil.runCycles( 100000000 );
@@ -145,8 +145,8 @@ def main():
     if(capMsg == readData):
         print ("Success - PSU get capabilities")
     else:
-        print capMsg
-        print readData
+        print(capMsg)
+        print(readData)
         raise Exception('data mistmach')
 
 if __name__ == "__main__":
diff --git a/src/test/testcases/testPSUReadSbeMem.py b/src/test/testcases/testPSUReadSbeMem.py
index 4f53a24e..d20192a9 100644
--- a/src/test/testcases/testPSUReadSbeMem.py
+++ b/src/test/testcases/testPSUReadSbeMem.py
@@ -22,7 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
-
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
@@ -88,7 +88,7 @@ def readSeeprom(offset, size, destAddr, primStatus, secStatus):
     # HOST->SBE data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data )
 
-    print "\n  Poll on Host side for INTR  ...\n"
+    print("\n  Poll on Host side for INTR  ...\n")
     #Poll on HOST DoorBell Register for interrupt
     regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 )
 
@@ -102,13 +102,13 @@ def main():
     # Run Simics initially
     testUtil.runCycles( 10000000 );
 
-    print "\n  Execute SBE Test - Read SBE Mem\n"
+    print("\n  Execute SBE Test - Read SBE Mem\n")
 
     '''
     Test Case 1
     '''
     readSeeprom(0, 128, 0x08000000, 0, 0)
-    print "SUCCESS: read seeprom valid"
+    print("SUCCESS: read seeprom valid")
 
     # Read data from cache and verify its contents
     # seeprom header
@@ -118,34 +118,34 @@ def main():
 
     for byte in range(len(seepprmHdr)):
         if( ord(seepprmHdr[byte]) != readData[byte ]):
-             print "Data mismtach at: ",  byte ;
-             print " expected: ", ord(seepprmHdr[byte]);
-             print " Actual: ", readData[byte];
+             print("Data mismtach at: ",  byte)
+             print(" expected: ", ord(seepprmHdr[byte]))
+             print(" Actual: ", readData[byte])
              raise Exception('data mistmach');
 
     '''
     Test Case 2
     '''
     readSeeprom(0x38CA0, 0x180, 0x8973780, 0, 0)
-    print "SUCCESS: read seeprom HB testcase"
+    print("SUCCESS: read seeprom HB testcase")
 
     '''
     Test Case 3
     '''
     readSeeprom(0x0, 0x40, 0x08000000, 0x03, 0x19)
-    print "SUCCESS: read seeprom size not aligned"
+    print("SUCCESS: read seeprom size not aligned")
 
     '''
     Test Case 4
     '''
     readSeeprom(0x3fe80, 0x180, 0x08000000, 0x03, 0x19)
-    print "SUCCESS: read seeprom size exceeded"
+    print("SUCCESS: read seeprom size exceeded")
 
     '''
     Test Case 5
     '''
     readSeeprom(0x7, 0x40, 0x08000000, 0x03, 0x19)
-    print "SUCCESS: read seeprom offset not aligned"
+    print("SUCCESS: read seeprom offset not aligned")
 
 if __name__ == "__main__":
     if testUtil.getMachineName() == "axone":
diff --git a/src/test/testcases/testPSUSetFFDCAddr.py b/src/test/testcases/testPSUSetFFDCAddr.py
index 5e64c6c6..14ea4c49 100644
--- a/src/test/testcases/testPSUSetFFDCAddr.py
+++ b/src/test/testcases/testPSUSetFFDCAddr.py
@@ -23,6 +23,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import testPSUUtil
 import testRegistry as reg
 import testUtil
@@ -86,7 +87,7 @@ def main():
     # Intialize the class obj instances
     regObj = testPSUUtil.registry() # Registry obj def for operation
 
-    print "\n  Execute SBE Test - Set FFDC Address\n"
+    print("\n  Execute SBE Test - Set FFDC Address\n")
 
     '''
     Test Case 1
@@ -94,7 +95,7 @@ def main():
     # HOST->SBE data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data )
 
-    print "\n  Poll on Host side for INTR  ...\n"
+    print("\n  Poll on Host side for INTR  ...\n")
     #Poll on HOST DoorBell Register for interrupt
     regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 )
 
diff --git a/src/test/testcases/testPSUSetStashPair.py b/src/test/testcases/testPSUSetStashPair.py
index 24918f55..69f02035 100644
--- a/src/test/testcases/testPSUSetStashPair.py
+++ b/src/test/testcases/testPSUSetStashPair.py
@@ -22,7 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
-
+from __future__ import print_function
 import sys
 import os
 import struct
@@ -186,80 +186,80 @@ def main():
     # Intialize the class obj instances
     regObj = testPSUUtil.registry() # Registry obj def for operation
 
-    print "\n  Execute SBE Test \n"
+    print("\n  Execute SBE Test \n")
     # HOST->SBE data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data1 )
-    print "\n  Poll on Host side for INTR  ...\n"
+    print("\n  Poll on Host side for INTR  ...\n")
     #Poll on HOST DoorBell Register for interrupt
     regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 )
     #SBE->HOST data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, host_test_data_success )
     testUtil.runCycles( 10000000 );
 
-    print "\n  Execute SBE Test \n"
+    print("\n  Execute SBE Test \n")
     # HOST->SBE data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data2 )
-    print "\n  Poll on Host side for INTR  ...\n"
+    print("\n  Poll on Host side for INTR  ...\n")
     #Poll on HOST DoorBell Register for interrupt
     regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 )
     #SBE->HOST data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, host_test_data_success )
     testUtil.runCycles( 10000000 );
 
-    print "\n  Execute SBE Test \n"
+    print("\n  Execute SBE Test \n")
     # HOST->SBE data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data3 )
-    print "\n  Poll on Host side for INTR  ...\n"
+    print("\n  Poll on Host side for INTR  ...\n")
     #Poll on HOST DoorBell Register for interrupt
     regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 )
     #SBE->HOST data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, host_test_data_success )
     testUtil.runCycles( 10000000 );
 
-    print "\n  Execute SBE Test \n"
+    print("\n  Execute SBE Test \n")
     # HOST->SBE data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data4 )
-    print "\n  Poll on Host side for INTR  ...\n"
+    print("\n  Poll on Host side for INTR  ...\n")
     #Poll on HOST DoorBell Register for interrupt
     regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 )
     #SBE->HOST data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, host_test_data_success )
     testUtil.runCycles( 10000000 );
 
-    print "\n  Execute SBE Test \n"
+    print("\n  Execute SBE Test \n")
     # HOST->SBE data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data5 )
-    print "\n  Poll on Host side for INTR  ...\n"
+    print("\n  Poll on Host side for INTR  ...\n")
     #Poll on HOST DoorBell Register for interrupt
     regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 )
     #SBE->HOST data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, host_test_data_success )
     testUtil.runCycles( 10000000 );
 
-    print "\n  Execute SBE Test \n"
+    print("\n  Execute SBE Test \n")
     # HOST->SBE data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data6 )
-    print "\n  Poll on Host side for INTR  ...\n"
+    print("\n  Poll on Host side for INTR  ...\n")
     #Poll on HOST DoorBell Register for interrupt
     regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 )
     #SBE->HOST data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, host_test_data_success )
     testUtil.runCycles( 10000000 );
 
-    print "\n  Execute SBE Test \n"
+    print("\n  Execute SBE Test \n")
     # HOST->SBE data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data7 )
-    print "\n  Poll on Host side for INTR  ...\n"
+    print("\n  Poll on Host side for INTR  ...\n")
     #Poll on HOST DoorBell Register for interrupt
     regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 )
     #SBE->HOST data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, host_test_data_success )
     testUtil.runCycles( 10000000 );
 
-    print "\n  Execute SBE Test \n"
+    print("\n  Execute SBE Test \n")
     # HOST->SBE data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data8 )
-    print "\n  Poll on Host side for INTR  ...\n"
+    print("\n  Poll on Host side for INTR  ...\n")
     #Poll on HOST DoorBell Register for interrupt
     regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 )
     #SBE->HOST data set execution
diff --git a/src/test/testcases/testPSUUserUtil.py b/src/test/testcases/testPSUUserUtil.py
index d6eac4af..86cd79b9 100644
--- a/src/test/testcases/testPSUUserUtil.py
+++ b/src/test/testcases/testPSUUserUtil.py
@@ -37,7 +37,7 @@
 #      1.0     gkeishin     29/03/16     Initial create
 #############################################################
 '''
-
+from __future__ import print_function
 import testPSUUtil
 
 '''
@@ -55,5 +55,5 @@ either SUCCESS or FAILURE as an end result for generalization purpose.
 ##########################################################################
 def classUtilFuncSample(i_paramArray):
     for input in i_paramArray:
-        print "  classUtilFuncSample : parm: ",input
+        print("  classUtilFuncSample : parm: ",input)
     return testPSUUtil.SUCCESS 
diff --git a/src/test/testcases/testPSUUtil.py b/src/test/testcases/testPSUUtil.py
index 0255b38f..c249ba09 100644
--- a/src/test/testcases/testPSUUtil.py
+++ b/src/test/testcases/testPSUUtil.py
@@ -40,6 +40,7 @@
 #-------------------------
 # Imports packages
 #-------------------------
+from __future__ import print_function
 import time
 import conf
 import testUtil
@@ -104,9 +105,9 @@ class registry(object):
     # Read Reg value set or updated
     #------------------------------
     def getRegData(self):
-        print "  Addr  : ",hex(self.regAddr)
-        print "  Value : ",self.regVal
-        print "  Size  : ",self.regSize
+        print("  Addr  : ",hex(self.regAddr))
+        print("  Value : ",self.regVal)
+        print("  Size  : ",self.regSize)
 
     #------------------------------
     # Write to a Registry
@@ -115,9 +116,9 @@ class registry(object):
         address = self.regAddr
         value   = self.stringToByte(self.regVal)
         size    = self.regSize
-#        print "  WData  : 0x%s -> Byte Data %s"% (self.regVal,value)
-#        print "  Addr   :", hex(address)
-#        print "  Size   : %s Bytes"% size
+#        print("  WData  : 0x%s -> Byte Data %s"% (self.regVal,value))
+#        print("  Addr   :", hex(address))
+#        print("  Size   : %s Bytes"% size)
 
         self.__write(objType,address,value,size)
         return
@@ -132,8 +133,8 @@ class registry(object):
         size = 8
         for i in range (entryCount):
             value = stringToByte(data[i])
-#            print "\n   Writting ", hex(REGDATA_SBE[i])
-#            print "   %x %x %x %x %x %x %x %x" % (value[0],value[1],value[2],value[3],value[4],value[5],value[6],value[7])
+#            print("\n   Writting ", hex(REGDATA_SBE[i]))
+#            print("   %x %x %x %x %x %x %x %x" % (value[0],value[1],value[2],value[3],value[4],value[5],value[6],value[7]))
             simObj.write(None, REGDATA_SBE[regIndex],
                         (value[0],value[1],value[2],value[3],value[4],value[5],value[6],value[7]),
                         size)
@@ -153,7 +154,7 @@ class registry(object):
             simObj.write(None, address,
                         (value[0],value[1],value[2],value[3],value[4],value[5],value[6],value[7]),
                         size)
-        print "  SIM obj: Write %s bytes [ OK ] " % size
+        print("  SIM obj: Write %s bytes [ OK ] " % size)
         return
 
     #---------------------------
@@ -164,9 +165,9 @@ class registry(object):
         size    = self.regSize
         value   = self.regVal
 #        if int(value) !=0:
-#            print "  RData  :", value
-#        print "  Addr   :", hex(address)
-#        print "  Size   : %s Bytes"% size
+#            print("  RData  :", value)
+#        print("  Addr   :", hex(address))
+#        print("  Size   : %s Bytes"% size)
 
         value = self.__read(objType,address,size)
         return value
@@ -183,20 +184,20 @@ class registry(object):
         value   = self.regVal     # Max lentgth it should read
 
         MaxAddr  = address + value   # This is the addres range it could read
-#        print "  MaxAddr Range:",hex(MaxAddr)
+#        print("  MaxAddr Range:",hex(MaxAddr))
         OffsetAddr = address
-#        print "  OffsetAddr:",hex(OffsetAddr)
+#        print("  OffsetAddr:",hex(OffsetAddr))
 
-#        print "  Memory Entries to be read : %d" % (value/8)
-#        print "  Match Magic Number : ", magicNum
+#        print("  Memory Entries to be read : %d" % (value/8))
+#        print("  Match Magic Number : ", magicNum)
 
         while ( OffsetAddr <= MaxAddr):
             sim_data = self.__read(objType,OffsetAddr,size)
-#            print " ", hex(OffsetAddr),self.joinListDataToHex(sim_data).upper()
+#            print(" ", hex(OffsetAddr),self.joinListDataToHex(sim_data).upper())
             OffsetAddr += 8
 
             if self.validateTestMemOp(sim_data,magicNum) == True:
-#                        print "  Test validated .. [ OK ]"
+#                        print("  Test validated .. [ OK ]")
                         return SUCCESS
 
         return FAILURE # Failed validation
@@ -207,7 +208,7 @@ class registry(object):
     def __read(self, Targetobj, address, size):
         simObj = SIM_get_interface(Targetobj, "memory_space")
         value = simObj.read(None, address, size, 0x0)
-        #print "  SIM obj: Read %s bytes [ OK ] " % size
+        #print("  SIM obj: Read %s bytes [ OK ] " % size)
         return value
 
     #--------------------------------
@@ -253,14 +254,14 @@ class registry(object):
         #--------------------------------------------
         for l_params in test_bucket:
         #--------------------------------------------
-#            print "  Desc   : %s "  % l_params[5]
-#            print "  Op     : %s "  % l_params[0]
+#            print("  Desc   : %s "  % l_params[5])
+#            print("  Op     : %s "  % l_params[0])
             if "func" == l_params[0]:
-                print "  Func    : %s "  % l_params[1]
+                print("  Func    : %s "  % l_params[1])
             if l_params[4] != "None":
-                print "  Expect : %s "  % l_params[4]
+                print("  Expect : %s "  % l_params[4])
             if "func" == l_params[0]:
-                print "  Function Params :",l_params[2]
+                print("  Function Params :",l_params[2])
             else:
                                   # addr,      value,      size
                 self.setRegData(l_params[1],l_params[2],l_params[3])
@@ -279,16 +280,16 @@ class registry(object):
                 '''
                 if l_params[4] != "None":
                     if self.validateTestOp(sim_data,l_params[4]) == True:
-                        print "  Test validated .. [ OK ]"
+                        print("  Test validated .. [ OK ]")
                     else:
-                        print "  ++++++++++++++++++++++++++++++++++++++++++"
-                        print "  simics Data  : ", sim_data
-                        print "  simics Hex   : ", self.joinListDataToHex(sim_data).upper()
+                        print("  ++++++++++++++++++++++++++++++++++++++++++")
+                        print("  simics Data  : ", sim_data)
+                        print("  simics Hex   : ", self.joinListDataToHex(sim_data).upper())
                         if(raiseException == True):
                             raise Exception('Data mistmach');
                         return FAILURE # Failed validation
 #                else:
-#                    print "  ++++++++++++++++++++++++++++++++++++++++++"
+#                    print("  ++++++++++++++++++++++++++++++++++++++++++")
             elif "write" == l_params[0]:
                 self.writeToReg(testOp)
             elif "memRead" == l_params[0]:
@@ -299,27 +300,27 @@ class registry(object):
                 rc = self.loadFunc( l_params[1], l_params[2] )
                 return rc
             else:
-                print "\n Invalid Test Data"
+                print("\n Invalid Test Data")
                 if(raiseException == True):
                     raise Exception('Invalid Test Data');
                 return FAILURE # Unknown entry op
 
-            print "\n"
+            print("\n")
         return SUCCESS
 
     #----------------------------------------------------
     # Validate simulator data against test data
     #----------------------------------------------------
     def validateTestOp(self, sim_data, test_data):
-        print "  Test Expects :  0x%s " % test_data
-        print "  Expect bytes : ", self.stringToByte(test_data)
+        print("  Test Expects :  0x%s " % test_data)
+        print("  Expect bytes : ", self.stringToByte(test_data))
         if self.compareList(self.stringToByte(test_data), sim_data, "None") == True:
-           print "  Test ... [ OK ] "
-           print "  ++++++++++++++++++++++++++++++++++++++++++"
+           print("  Test ... [ OK ] ")
+           print("  ++++++++++++++++++++++++++++++++++++++++++")
            return SUCCESS
         else:
-           print "  Test Failed... !!!"
-           print "  ++++++++++++++++++++++++++++++++++++++++++"
+           print("  Test Failed... !!!")
+           print("  ++++++++++++++++++++++++++++++++++++++++++")
            return FAILURE
 
     #----------------------------------------------------
@@ -338,11 +339,11 @@ class registry(object):
     def compareList(self, expList, resList, opType):
         for i in range(0,8):
             if int(expList[i]) == int(resList[i]):
-                #print "  %s : %s  " % (expList[i],resList[i])
+                #print("  %s : %s  " % (expList[i],resList[i]))
                 continue
             else:
                 if opType != "memRead":
-                    print "  Error \t  %s : %s  [ Mismatch ]" % (expList[i],resList[i])
+                    print("  Error \t  %s : %s  [ Mismatch ]" % (expList[i],resList[i]))
                     return False # mismatch
                 return # Return nothing for Next Mem byte read
         return True
@@ -359,7 +360,7 @@ class registry(object):
                 if rc == SUCCESS:
                     break
                 elif retries <= 0:
-                    print "  Retrials exhausted... Exiting polling"
+                    print("  Retrials exhausted... Exiting polling")
                     raise Exception('Polling Failed for - ' + l_param[5]);
                     break
                 else:
diff --git a/src/test/testcases/testPsuHostPassThrough.py b/src/test/testcases/testPsuHostPassThrough.py
index 6fa3126f..789a216b 100644
--- a/src/test/testcases/testPsuHostPassThrough.py
+++ b/src/test/testcases/testPsuHostPassThrough.py
@@ -22,7 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
-
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
@@ -98,7 +98,7 @@ def main():
     # Intialize the class obj instances
     regObj = testPSUUtil.registry() # Registry obj def for operation
 
-    print "\n  Execute SBE Test - Set Pass through Address\n"
+    print("\n  Execute SBE Test - Set Pass through Address\n")
 
     '''
     Test Case 1
@@ -106,7 +106,7 @@ def main():
     # HOST->SBE data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data )
 
-    print "\n  Poll on Host side for INTR  ...\n"
+    print("\n  Poll on Host side for INTR  ...\n")
     #Poll on HOST DoorBell Register for interrupt
     regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 )
 
@@ -126,8 +126,8 @@ def main():
     if(data == readData):
         print ("Success - Write-Read PBA - With Pass through Mode")
     else:
-        print data
-        print readData
+        print(data)
+        print(readData)
         raise Exception('data mistmach')
     # Send an invalid size, it should fail
     testMemUtil.getmem_failure(0x00000000, 128*4, 0x102, 0x0002000a)
diff --git a/src/test/testcases/testPutGetRegFpr.py b/src/test/testcases/testPutGetRegFpr.py
index cf1a4c84..01961b34 100755
--- a/src/test/testcases/testPutGetRegFpr.py
+++ b/src/test/testcases/testPutGetRegFpr.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
diff --git a/src/test/testcases/testPutGetRegGpr.py b/src/test/testcases/testPutGetRegGpr.py
index 7fa24669..aacc0576 100755
--- a/src/test/testcases/testPutGetRegGpr.py
+++ b/src/test/testcases/testPutGetRegGpr.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
diff --git a/src/test/testcases/testPutGetRegSpr.py b/src/test/testcases/testPutGetRegSpr.py
index 2b4f793c..c13770ef 100755
--- a/src/test/testcases/testPutGetRegSpr.py
+++ b/src/test/testcases/testPutGetRegSpr.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
diff --git a/src/test/testcases/testPutMem_fail.py b/src/test/testcases/testPutMem_fail.py
index 762b64ac..9a538d9c 100644
--- a/src/test/testcases/testPutMem_fail.py
+++ b/src/test/testcases/testPutMem_fail.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
diff --git a/src/test/testcases/testQuiesce.py b/src/test/testcases/testQuiesce.py
index 5353d40e..f396170e 100755
--- a/src/test/testcases/testQuiesce.py
+++ b/src/test/testcases/testQuiesce.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
diff --git a/src/test/testcases/testRunTillSbeBooted.py b/src/test/testcases/testRunTillSbeBooted.py
index 16b7a475..b56c0c74 100644
--- a/src/test/testcases/testRunTillSbeBooted.py
+++ b/src/test/testcases/testRunTillSbeBooted.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import os
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
@@ -41,11 +42,11 @@ else:
 while True:
     try:
         if testUtil.read(lbus, 0x2824, 4)[0] & 0x80 :
-            print "SBE is booted, continue"
+            print("SBE is booted, continue")
             break
         else:
-            print "SBE is still not booted"
+            print("SBE is still not booted")
 
     except:
-        print "."
+        print(".")
     testUtil.runCycles( 10000000 )
diff --git a/src/test/testcases/testSbeDump.py b/src/test/testcases/testSbeDump.py
index 8e92f07d..8501ca24 100644
--- a/src/test/testcases/testSbeDump.py
+++ b/src/test/testcases/testSbeDump.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest")
 sys.path.append("targets/p9_axone/sbeTest" )
@@ -93,7 +94,7 @@ def main():
         #read user data id
         data = testUtil.readDsEntryReturnVal()
         id = (data[0] << 8) | data[1]
-        print "User data Id ["+str(hex(id))+"]"
+        print("User data Id ["+str(hex(id))+"]")
         len = (data[2] << 8) | data[3]
         #if it is trace field SBE_FFDC_TRACE_DUMP
         fileName = ""
diff --git a/src/test/testcases/testSecurity.py b/src/test/testcases/testSecurity.py
index d4e3efaf..6b019666 100644
--- a/src/test/testcases/testSecurity.py
+++ b/src/test/testcases/testSecurity.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import os
 import sys
 import struct
@@ -92,23 +93,23 @@ def main():
                         whitelist_table1,
                         whitelist_table2,
                         whitelist_table3)
-            print "generated whitelist validation passed"
+            print("generated whitelist validation passed")
             test_normal('blacklist',
                         blacklist,
                         blacklist_table1,
                         blacklist_table2,
                         blacklist_table3)
-            print "generated blacklist validation passed"
+            print("generated blacklist validation passed")
 
         # getscom success
         testScomUtil.getscom(0x0204001A)
-        print "getscom success testcase - passed"
+        print("getscom success testcase - passed")
         # getscom failure
         testScomUtil.getscom(eval(BLACKLISTED_REG_FOR_READ_TEST), [0x00, 0x05, 0x00, 0x23])
-        print "getscom failure testcase - passed"
+        print("getscom failure testcase - passed")
         # putscom success
         testScomUtil.putscom(eval(WHITELISTED_REG_FOR_WRITE_TEST), testScomUtil.getscom(eval(WHITELISTED_REG_FOR_WRITE_TEST)))
-        print "putscom success testcase - passed"
+        print("putscom success testcase - passed")
         # putscom failure
         while(True):
             random_addr = struct.unpack('>L', os.urandom(4))[0]
@@ -116,21 +117,21 @@ def main():
                 if not ((random_addr & 0x80000000) or (random_addr & 0x00F00000)):
                     testScomUtil.putscom(random_addr, 0, [0x00, 0x05, 0x00, 0x23])
                     break
-        print "putscom failure testcase - passed"
+        print("putscom failure testcase - passed")
         # modify scom success
         dataWritten = testScomUtil.getscom(0x00040006)
         testScomUtil.modifyScom(0x01, 0x00040006, 0x0)
         dataRead = testScomUtil.getscom(0x00040006)
         if(dataRead != dataWritten):
             raise Exception('modify scom failed %x != %x' % (dataRead, dataWritten))
-        print "modify scom success testcase - passed"
+        print("modify scom success testcase - passed")
         # putscom under mask success
         dataWritten = testScomUtil.getscom(0x00040006)
         testScomUtil.putScomUnderMask(0x00040006, dataWritten, 0xFFFFFFFFFFFFFFFF)
         dataRead = testScomUtil.getscom(0x00040006)
         if(dataRead != dataWritten):
             raise Exception('PutScom under mask failed %x != %x' % (dataRead, dataWritten))
-        print "putscom under mask success testcase - passed"
+        print("putscom under mask success testcase - passed")
 
         # Greylist test cases
         dataWritten = testScomUtil.getscom(0x0901080B)
@@ -142,7 +143,7 @@ def main():
         testScomUtil.putScomUnderMask(0x0901080B, dataWritten, 0xFF0FFFFFFF0FFFFF)
         # Do putScomUnderMask with superset mask
         testScomUtil.putScomUnderMask(0x0901080B, dataWritten, 0xFF00FFFFFF0FFFFF)
-        print "Greylist testcases - passed"
+        print("Greylist testcases - passed")
 
         # indirect scom test
         dataWritten = testScomUtil.getscom(0x8000000D06010C3F)
@@ -151,7 +152,7 @@ def main():
         dataRead = testScomUtil.getscom(0x8000000D06010C3F)
         if(dataRead != dataWritten):
             raise Exception('indirect scom test failed %x != %x' % (dataRead, dataWritten))
-        print "Indirect scom success testcase - passed"
+        print("Indirect scom success testcase - passed")
 
     except Exception, error:
         raise Exception(error)
@@ -164,11 +165,11 @@ def test_normal(id, list, table1, table2, table3):
                                table1,
                                table2,
                                table3)):
-            print id, list
-            print 'table1:', table1
-            print 'table2:', table2
-            print 'table3:', table3
-            print "Failed Addr", hex(addr)
+            print(id, list)
+            print('table1:', table1)
+            print('table2:', table2)
+            print('table3:', table3)
+            print("Failed Addr", hex(addr))
             raise Exception(id+' positive testcase')
     # negative testcase - number of random addresses checked is configurable
     i = 0
@@ -179,11 +180,11 @@ def test_normal(id, list, table1, table2, table3):
             i = i-1
         else:
             if(True == is_present(random_addr, table1, table2, table3)):
-                print id, list
-                print 'table1:', table1
-                print 'table2:', table2
-                print 'table3:', table3
-                print "Failed Addr", hex(random_addr)
+                print(id, list)
+                print('table1:', table1)
+                print('table2:', table2)
+                print('table3:', table3)
+                print("Failed Addr", hex(random_addr))
                 raise Exception(id+' negative testcase')
 
 def test_brute_force(id, list, table1, table2, table3):
@@ -196,18 +197,18 @@ def test_brute_force(id, list, table1, table2, table3):
             sys.stdout.write("Progress: addr[0x%08x] last_addr[0x%08x]" % (addr, last_addr) )
             sys.stdout.flush()
             if(True == is_present(addr, table1, table2, table3)):
-                print id, list
-                print 'table1:', table1
-                print 'table2:', table2
-                print 'table3:', table3
-                print "Failed Addr", hex(addr)
+                print(id, list)
+                print('table1:', table1)
+                print('table2:', table2)
+                print('table3:', table3)
+                print("Failed Addr", hex(addr))
                 raise Exception(id+' brute force testcase')
         addr = addr + 1
 
 def is_present(addr, table1, table2, table3):
     t1_addr = (addr & 0xFF000000) >> 24;
     if(DEBUG):
-        print "find", t1_addr, "in table1"
+        print("find", t1_addr, "in table1")
     for id1, (chiplet_range, count) in enumerate(table1):
         start = (chiplet_range & 0xFF00) >> 8
         end = chiplet_range & 0x00FF
@@ -219,7 +220,7 @@ def is_present(addr, table1, table2, table3):
             last_t2 = count-1
             t2_addr = (addr & 0x00FF0000) >> 16;
             if(DEBUG):
-                print "find", t2_addr, "in table2", first_t2, last_t2
+                print("find", t2_addr, "in table2", first_t2, last_t2)
             (found, id2) = binary_search(t2_addr, table2, first_t2, last_t2, True)
             if(found):
                 if(id2-1 < 0):
@@ -229,11 +230,11 @@ def is_present(addr, table1, table2, table3):
                 last_t3 = table2[id2][1]-1
                 t3_addr = (addr & 0x0000FFFF)
                 if(DEBUG):
-                    print "find",t3_addr,"in table3", first_t3, last_t3
+                    print("find",t3_addr,"in table3", first_t3, last_t3)
                 (found, id3) = binary_search(t3_addr, table3, first_t3, last_t3)
                 if(found):
                     if(DEBUG):
-                        print "found"
+                        print("found")
                     return True
     return False
 
diff --git a/src/test/testcases/testSecurityListDump.py b/src/test/testcases/testSecurityListDump.py
index 78d3eda3..f8f1474f 100644
--- a/src/test/testcases/testSecurityListDump.py
+++ b/src/test/testcases/testSecurityListDump.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import testPSUUtil
 import testRegistry as reg
 import testUtil
@@ -76,7 +77,7 @@ def main():
     regObj = testPSUUtil.registry() # Registry obj def for operation
 
     testUtil.runCycles( 1000000 );
-    print "\n  Execute SBE Test [ System Fabric Map ] ...\n"
+    print("\n  Execute SBE Test [ System Fabric Map ] ...\n")
 
     '''
     Test Case 1
@@ -84,7 +85,7 @@ def main():
     # HOST->SBE data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data )
 
-    print "\n  Poll on Host side for INTR  ...\n"
+    print("\n  Poll on Host side for INTR  ...\n")
     #Poll on HOST DoorBell Register for interrupt
     regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 )
 
diff --git a/src/test/testcases/testSram.py b/src/test/testcases/testSram.py
index 0ec9c018..fc3c08bd 100644
--- a/src/test/testcases/testSram.py
+++ b/src/test/testcases/testSram.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 import os
 sys.path.append("targets/p9_nimbus/sbeTest" )
@@ -80,8 +81,8 @@ def getsram(addr, mode, length, primStatus, secStatus):
         data += list(testUtil.readDsEntryReturnVal())
     readLen = testUtil.readDsEntryReturnVal()
     if(getsingleword(length) != list(readLen)):
-        print getsingleword(length)
-        print list(readLen)
+        print(getsingleword(length))
+        print(list(readLen))
         raise Exception("Invalid Length")
 
     expResp = (getsingleword(0xc0dea403)
@@ -111,8 +112,8 @@ def main( ):
         if(data == readData):
             print("Success: put - get sram")
         else:
-            print data
-            print readData
+            print(data)
+            print(readData)
             raise Exception('data mistmach')
 
         # secure mem - write to disallowed mem
@@ -155,7 +156,7 @@ def main( ):
         #testUtil.readDsFifo( GETSRAM_OCC_EXPDATA_1 )
         #testUtil.readEot( )
     except:
-        print "FAILED Test Case:"+str(testcase)
+        print("FAILED Test Case:"+str(testcase))
         raise Exception('Failure')
 
 #-------------------------------------------------
diff --git a/src/test/testcases/testStartInstruction.py b/src/test/testcases/testStartInstruction.py
index e2c5e1c2..e65c3744 100644
--- a/src/test/testcases/testStartInstruction.py
+++ b/src/test/testcases/testStartInstruction.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
diff --git a/src/test/testcases/testStopClocks.py b/src/test/testcases/testStopClocks.py
index 5df9cb91..5b452665 100644
--- a/src/test/testcases/testStopClocks.py
+++ b/src/test/testcases/testStopClocks.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
diff --git a/src/test/testcases/testStopInstruction.py b/src/test/testcases/testStopInstruction.py
index 37c77900..ca31457e 100644
--- a/src/test/testcases/testStopInstruction.py
+++ b/src/test/testcases/testStopInstruction.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
diff --git a/src/test/testcases/testSuspendIO.py b/src/test/testcases/testSuspendIO.py
index 09d1250b..48257f69 100755
--- a/src/test/testcases/testSuspendIO.py
+++ b/src/test/testcases/testSuspendIO.py
@@ -22,7 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
-
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 sys.path.append("targets/p9_axone/sbeTest" )
diff --git a/src/test/testcases/testSystemFabricMap.py b/src/test/testcases/testSystemFabricMap.py
index d97105fe..c5adabc5 100644
--- a/src/test/testcases/testSystemFabricMap.py
+++ b/src/test/testcases/testSystemFabricMap.py
@@ -22,7 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
-
+from __future__ import print_function
 import testPSUUtil
 import testRegistry as reg
 import testUtil
@@ -77,7 +77,7 @@ def main():
     regObj = testPSUUtil.registry() # Registry obj def for operation
 
     testUtil.runCycles( 1000000 );
-    print "\n  Execute SBE Test [ System Fabric Map ] ...\n"
+    print("\n  Execute SBE Test [ System Fabric Map ] ...\n")
 
     '''
     Test Case 1
@@ -85,7 +85,7 @@ def main():
     # HOST->SBE data set execution
     regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data )
 
-    print "\n  Poll on Host side for INTR  ...\n"
+    print("\n  Poll on Host side for INTR  ...\n")
     #Poll on HOST DoorBell Register for interrupt
     regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 )
 
diff --git a/src/test/testcases/testTraceArray.py b/src/test/testcases/testTraceArray.py
index 030719e4..57cecbcf 100644
--- a/src/test/testcases/testTraceArray.py
+++ b/src/test/testcases/testTraceArray.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 sys.path.append("targets/p9_nimbus/sbeTest" )
 import testUtil
diff --git a/src/test/testcases/testUnsecureMemRegions.py b/src/test/testcases/testUnsecureMemRegions.py
index a0b0d21f..fa56f9f4 100644
--- a/src/test/testcases/testUnsecureMemRegions.py
+++ b/src/test/testcases/testUnsecureMemRegions.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import sys
 import os
 import struct
diff --git a/src/test/testcases/testUtil.py b/src/test/testcases/testUtil.py
index 95626fa1..d070081e 100644
--- a/src/test/testcases/testUtil.py
+++ b/src/test/testcases/testUtil.py
@@ -22,6 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+from __future__ import print_function
 import time
 import conf
 from sim_commands import *
@@ -252,14 +253,14 @@ def runCycles( cycles ):
         syscmd   =   "run-cycles %d"%(cycles)
         ( rc, out )  =   quiet_run_command( syscmd, output_modes.regular )
         if ( rc ):
-            print "simics ERROR running %s: %d "%( syscmd, rc )
+            print("simics ERROR running %s: %d "%( syscmd, rc ))
 
 def checkEqual( data, expdata ):
     """ Throw exception if data is not equal """
     if( cmp(data, expdata )):
-        print "Eqality check failed"
-        print "Data:", data
-        print "Expected Data", expdata
+        print("Eqality check failed")
+        print("Data:", data)
+        print("Expected Data", expdata)
         raise Exception('data mistmach');
 
 def getMachineName():
@@ -277,4 +278,4 @@ def collectFFDC():
         simics.SIM_run_command('sbe-regffdc 0')
         simics.SIM_run_command('backplane0.proc0.pib_cmp.sbe_ppe->ppe_state')
         simics.SIM_run_command('backplane0.proc0.cfam_cmp.sbe_fifo->upstream_hw_fifo')
-        simics.SIM_run_command('backplane0.proc0.cfam_cmp.sbe_fifo->downstream_hw_fifo')
\ No newline at end of file
+        simics.SIM_run_command('backplane0.proc0.cfam_cmp.sbe_fifo->downstream_hw_fifo')