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-rw-r--r--src/test/testcases/testAduMem_itag.py13
1 files changed, 7 insertions, 6 deletions
diff --git a/src/test/testcases/testAduMem_itag.py b/src/test/testcases/testAduMem_itag.py
index 1172ef94..9ea72572 100644
--- a/src/test/testcases/testAduMem_itag.py
+++ b/src/test/testcases/testAduMem_itag.py
@@ -22,6 +22,7 @@
# permissions and limitations under the License.
#
# IBM_PROLOG_END_TAG
+from __future__ import print_function
import sys
sys.path.append("targets/p9_nimbus/sbeTest" )
sys.path.append("targets/p9_axone/sbeTest" )
@@ -57,8 +58,8 @@ def main( ):
if(data == readData):
print ("Success - Write-Read ADU with Itag")
else:
- print data
- print readData
+ print(data)
+ print(readData)
raise Exception('data mistmach')
# Partial Write test
@@ -72,10 +73,10 @@ def main( ):
if(sandwichData == readBackData):
print ("Success - Write_Part-Read ADU with Itag")
else:
- print readData
- print data
- print readBackData
- print sandwichData
+ print(readData)
+ print(data)
+ print(readBackData)
+ print(sandwichData)
raise Exception('data mistmach')
#-------------------------------------------------
# Calling all test code
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