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* aspeed/ast-scu.c: add ast_get_m_pll_clk() for AST_SOC_G5David Thompson2019-04-041-0/+1
| | | | | | | | | | | | | This code change adds the AST_SOC_G5 version of ast_get_m_pll_clk(), which is relevant to AST1520, AST2500, and AST3200 devices. This change properly enables the AST_SOC_G5 logic in print_cpuinfo(), which can be turned on by defining CONFIG_DISPLAY_CPUINFO. Signed-off-by: David Thompson <dthompson@mellanox.com> Reviewed-by: Shravan Ramani <sramani@mellanox.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* arch-aspeed: Make AHBC and SDMC header guards uniqueAndrew Jeffery2018-07-242-4/+4
| | | | | | | | Otherwise we get mysterious missing symbols if we include both those and the ast-{ahbc,sdmc}.h files. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* aspeed: Add defines for all watchdogsJoel Stanley2017-06-262-2/+5
| | | | | | | This adds defines for WDT2 (and WDT3 for the ast2500), and renames the existing one to WDT1. Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: AST2500: add supportJoel Stanley2016-07-2711-0/+1490
| | | | | | Extracted from ast_sdk.v00.03.21 which is based on u-boot v2013. Signed-off-by: Joel Stanley <joel@jms.id.au>
* arm: Fix setjmp (again)Alexander Graf2016-07-081-1/+3
| | | | | | | | | | | | Commit e677724 (arm: Fix setjmp) added code to fix compilation of the setjmp code path with thumv1. Unfortunately it missed a constraint that the adr instruction can only refer to 4 byte aligned offsets. So this patch adds the required alignment hooks to make compilation work again even when setjmp doesn't happen to be 4 byte aligned. Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: Tom Rini <trini@konsulko.com>
* sunxi: Add missing boot_media fields in the SPL headerOlliver Schinagl2016-07-021-0/+2
| | | | | | | | | | | Commit b19236fd1 ("sunxi: Increase SPL header size to 64 bytes to avoid code corruption") Added defines for MMC0 and SPI as boot identification. After verifying on an OLinuXino Lime2 with NAND and eMMC, the expected values have been confirmed and added to spl.h Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-06-282-14/+14
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| * armv8: fsl-layerscape: Append "A" in SoC name for ARM based SoCsPrabhakar Kushwaha2016-06-282-14/+14
| | | | | | | | | | | | | | | | | | | | | | Freescale ARMv8 SoC name ends with "A" to represent ARM SoCs. like LS2080A, LS1043A, LS1012A. So append "A" to SoC names. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | arm: bcm235xx: implement the boot0 hook codeSteve Rae2016-06-241-0/+15
|/ | | | | | Choose the Kconfig boot0 hook option and implement the required code. Signed-off-by: Steve Rae <srae@broadcom.com>
* sunxi: Add base address for GICChen-Yu Tsai2016-06-201-0/+2
| | | | | | | | | Instead of hardcoding the GIC addresses in the PSCI implementation, provide a base address in the cpu header. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add CPUCFG debug lock and sun7i cpu power controlsChen-Yu Tsai2016-06-201-1/+6
| | | | | | | | | | | | CPUCFG has an unlisted debug control register, which is used to disable external debug access. Also, sun7i secondary core power controls are in CPUCFG, as there's no separate PRCM block. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Group cpu core related controls togetherChen-Yu Tsai2016-06-202-24/+16
| | | | | | | | | | | | | Instead of listing individual registers for controls to each processor core, list them as an array of registers. This makes accessing controls by core index easier. Also rename "cpucfg_sun6i.h" (which was unused anyway) to the more generic "cpucfg.h", and add packed attribute to struct sunxi_cpucfg. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add missing linux/types.h header for cpucfg_sun6i.hChen-Yu Tsai2016-06-201-0/+2
| | | | | | | | | cpucfg_sun6i.h includes a register definition for the CPUCFG register block. The types used are u32 and u8, which are defined in linux/types.h. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add packed attribute to struct sunxi_prcm_regChen-Yu Tsai2016-06-201-1/+3
| | | | | | | | | struct sunxi_prcm_reg is a representation of the PRCM registers. Add the packed attribute to prevent the compiler from doing funny things. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Make CPUCFG_BASE macro names the same across familiesChen-Yu Tsai2016-06-201-2/+13
| | | | | | | | | Use SUNXI_CPUCFG_BASE across all families. This makes writing common PSCI code easier. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* ARM: PSCI: export common PSCI function declarations for C codeChen-Yu Tsai2016-06-201-0/+7
| | | | | | | | | | | Some common PSCI functions are written in assembly, but it should be possible to use them from C code. Add function declarations for C code to consume. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* clk: convert API to match reset/mailbox styleStephen Warren2016-06-191-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-06-183-0/+8
|\ | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
| * usb: xhci: fsl: Add workaround for USB erratum A008751Sriram Dash2016-06-131-0/+1
| | | | | | | | | | | | | | | | | | This patch is doing the following: 1. Implementing the errata for LS2080. 2. Adding fixup for fdt for LS2080. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
| * arm64: fsl-layerscape: add get_svr and IS_SVR_REV helperSriram Dash2016-06-133-0/+7
| | | | | | | | | | | | | | | | Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
* | arm: Fix setjmpAlexander Graf2016-06-171-5/+4
| | | | | | | | | | | | | | | | | | | | The setjmp/longjmp implementation did not work on thumb1 implementations because it used instruction encodings that don't exist on thumb1 yet. This patch limits itself to thumb1 instruction set for 32bit arm and removes a superfluous printf along the way. Signed-off-by: Alexander Graf <agraf@suse.de>
* | armv8: s32v234: Introduce basic support for s32v234evbEddy Petrișor2016-06-139-0/+1318
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial support for NXP's S32V234 SoC and S32V234EVB board. The S32V230 family is designed to support computation-intensive applications for image processing. The S32V234, as part of the S32V230 family, is a high-performance automotive processor designed to support safe computation-intensive applications in the area of vision and sensor fusion. Code originally writen by: Original-signed-off-by: Stoica Cosmin-Stefan <cosminstefan.stoica@freescale.com> Original-signed-off-by: Mihaela Martinas <Mihaela.Martinas@freescale.com> Original-signed-off-by: Eddy Petrișor <eddy.petrisor@gmail.com> Signed-off-by: Eddy Petrișor <eddy.petrisor@nxp.com>
* | board: arm:: Add support for Broadcom BCM23550Steve Rae2016-06-132-0/+46
| | | | | | | | | | | | Add support for the Broadcom BCM23550 board. Signed-off-by: Steve Rae <srae@broadcom.com>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-06-121-0/+5
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| * | sunxi: Downclock AHB1 to 100MHz on Allwinner A64Siarhei Siamashka2016-06-101-0/+5
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the AHB1 clock speed is configured as 200MHz by the SPL, but this causes a subtle and hard to reproduce data corruption in SRAM C (for example, this can't be easily detected with a trivial memset/memcmp test). For what it's worth, the Allwinner's BSP configures AHB1 as 200MHz, as can be verified by running the devmem2 tool in the system running the Allwinner's kernel 3.10.x: 0x1C20028: PLL_PERIPH0_CTRL_REG = 0x90041811 0x1C20054: AHB1_APB1_CFG_REG = 0x3180 0x1C20058: APB2_CFG_REG = 0x1000000 0x1C2005C: AHB2_CFG_REG = 0x1 However the FEL mode uses more conservative settings (100MHz for AHB1): 0x1C20028: PLL_PERIPH0_CTRL_REG = 0x90041811 0x1C20054: AHB1_APB1_CFG_REG = 0x3190 0x1C20058: APB2_CFG_REG = 0x1000000 0x1C2005C: AHB2_CFG_REG = 0x0 It is yet to be confirmed whether faster AHB1/AHB2 clock settings can be used safely if we initialize the AXP803 PMIC instead of using reset defaults. But in order to resolve the data corruption problem right now, it's best to downclock AHB1 to a safe level. Note that this issue only affects the SPL, which is not fully supported on Allwinner A64 yet and it should not affect the boot0 usage (unless somebody can confirm SRAM C corruption with the boot0 too). Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-06-121-0/+8
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| * | imx-common: introduce simpler macros for runtime dectionPeng Fan2016-05-241-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Introduce simpler macros for runtime cpu dection. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* | | armv8: ls2080aqds: Enable QSPI boot supportYuan Yao2016-06-101-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds QSPI boot support for LS2080AQDS board. The QSPI boot image need to be programmed into the QSPI flash first. Then we can switch to booting from QSPI memory space. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND bootYuan Yao2016-06-101-0/+2
| | | | | | | | | | | | | | | Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | armv8: ls2080aqds: Select QSPI CLK div via SCFGYuan Yao2016-06-101-0/+1
| | | | | | | | | | | | | | | | | | | | | QSPI module output SCLK divisor value is configured through SCFG. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | armv8/ls2080a: configure PMU's PCTBENR to enable WDTYunhui Cui2016-06-101-0/+1
| |/ |/| | | | | | | | | | | | | | | The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | arm, am335x: Enable Spread Spectrum for the MPUHeiko Schocher2016-06-092-1/+3
| | | | | | | | | | | | | | | | Enable Spread Spectrum for the MPU by calculating the required values and setting the registers accordingly. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* | am335x: add some missing CM_CLKMODE_DPLL_SSC macrosHeiko Schocher2016-06-091-0/+3
| | | | | | | | | | | | | | | | | | | | add missing CM_CLKMODE_DPLL_SSC_ACK_MASK, CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK and CM_CLKMODE_DPLL_SSC_TYPE_MASK defines. Used for enabling spread spectrum. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm, am335x: add some missing GPIO register definitionsHeiko Schocher2016-06-091-0/+2
| | | | | | | | | | | | | | | | | | add missing: OMAP_GPIO_IRQSTATUS_SET_0 and OMAP_GPIO_IRQSTATUS_SET_1 registers. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm/arm64: implement a boot header capabilityAndre Przywara2016-06-062-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SPL loaders (like Allwinner's boot0, and Broadcom's boot0) require a header before the actual U-Boot binary to both check its validity and to find other data to load. Sometimes this header may only be a few bytes of information, and sometimes this might simply be space that needs to be reserved for a post-processing tool. Introduce a config option to allow assembler preprocessor commands to be inserted into the code at the appropriate location; typical assembler preprocessor commands might be: .space 1000 .word 0x12345678 Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Steve Rae <srae@broadcom.com> Commit Notes: Please note that the current code: start.S (arm64) and vectors.S (arm) already jumps over some portion of data already, so this option basically just increases the size of this region (and the resulting binary). For use with Allwinner's boot0 blob there is a tool called boot0img[1], which fills the header to allow booting A64 based boards. For the Pine64 we need a 1536 byte header (including the branch instruction) at the moment, so we add this to the defconfig. [1] https://github.com/apritzel/pine64/tree/master/tools END Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: Introduce setjmp/longjmpAlexander Graf2016-06-061-0/+99
| | | | | | | | | | | | | | | | | | | | | | To quit an EFI application we will need logic to jump to the caller of a function without returning from the function we called into, so we need setjmp/longjmp functionality. This patch introduces a trivial implementation of these that I verified works on armv7, thumb2 and aarch64. Signed-off-by: Alexander Graf <agraf@suse.de>
* | Fix to davinci_nand.h to place CEnCFG registers at correctPeter Howard2016-06-061-4/+6
| | | | | | | | Signed-off-by: Peter Howard <phoward@gme.net.au>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-06-046-1/+47
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| * | armv8: fsl-layerscape: Add support of QorIQ LS1012A SoCPrabhakar Kushwaha2016-06-036-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. This patch add support of LS1012A SoC along with - Update platform & DDR clock read logic as per SVR - Define MMDC controller register set. - Update LUT base address for PCIe - Avoid L3 platform cache compilation - Update USB address, errata - SerDes table - Added CSU IDs for SDHC2, SAI-1 to SAI-4 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: Avoid LS1043A specifc definesPrabhakar Kushwaha2016-06-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Other than LS1043A, LS1012A also Chassis Gen2 Architecture compliant. So Avoid LS1043A specific defines in arch/arm Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2016-06-038-996/+30
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| * | | ARM: tegra: add core Tegra186 supportStephen Warren2016-05-312-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the bare minimum code to support Tegra186, with UART and eMMC working. The empty gpio.h is required because <asm/gpio.h> includes it. A future cleanup round may be able to solve this for all Tegra generations at once. mach-tegra/Makefile is adjusted not to compile anything for Tegra186, but instead to defer everything to mach-tegra/tegra186/Makefile. This allows the SoC code to pick-and-choose which of the C files in the "common" mach-tegra/ directory to compile in based on the SoC's needs. Most of the code is not valid for Tegra186, and this approach removes the need for mach-tegra/Makefile to contain many SoC-specific ifdefs. This approach may be applied to all other Tegra SoCs in a future cleanup round. board186.c is introduced to replace board.c and board2.c. These files currently contain a slew of SoC- and board-specific code that is not valid for Tegra186. This approach avoids adding yet more ifdefs to those files. A future cleanup round may refactor most of board*.c into board-/ SoC-specific functions files thus allowing the top-level functions like board_init_early_f to be shared again. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | mmc: tegra: add basic Tegra186 supportStephen Warren2016-05-311-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra186's MMC controller needs to be explicitly identified. Add another compatible value for it. Tegra186 will use an entirely different clock/reset control mechanism to existing chips, and will use standard clock/reset APIs rather than the existing Tegra-specific custom APIs. The driver support for that isn't ready yet, so simply disable all clock/reset usage if compiling for Tegra186. This must happen at compile time rather than run-time since the custom APIs won't even be compiled in on Tegra186. In the long term, the plan would be to convert the existing custom APIs to standard APIs and get rid of the ifdefs completely. The system's main eMMC will work without any clock/reset support, since the firmware will have already initialized the controller in order to load U-Boot. Hence the driver is useful even in this apparently crippled state. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: use DT bindings for GPIO namingStephen Warren2016-05-315-996/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | There are currently many places that define the list of all Tegra GPIOs; the DT binding header and custom Tegra-specific header file gpio.h. Fix the redundancy by replacing everything with the DT binding header file. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | arm: omap: Introduce vcores_init functionKeerthy2016-06-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The pmic registers for variants of am57xx boards are different hence we need to assign them carefully based on the board type. Add a function to assign omap_vcores after the board detection. Signed-off-by: Keerthy <j-keerthy@ti.com>
* | | ARM: DRA7: Add macros for voltage values for all OPPsAnna, Suman2016-06-021-6/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define specific macros for the voltage values for all voltage domains for all applicable OPPs - OPP_NOM, OPP_OD and OPP_HIGH. No separate macros are defined for VD_MPU and VD_CORE at OPP_OD and OPP_HIGH as these use the same values as OPP_NOM. The current macros will be used as common macros that can be redefined appropriately based on a selected OPP configuration at build time. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: DRA7: Consolidate voltage macros across different SoCsAnna, Suman2016-06-021-13/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The voltage values for each voltage domain at an OPP is identical across all the SoCs in the DRA7 family. The current code defines one set of macros for DRA75x/DRA74x SoCs and another set for DRA72x macros. Consolidate both these sets into a single set. This is done so as to minimize the number of macros used when voltage values will be added for other OPPs as well. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: DRA7: Define common macros for efuse register offsetsAnna, Suman2016-06-021-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define a set of common macros for the efuse register offsets (different for each OPP) that are used to get the AVS Class 0 voltage values and ABB configuration values. Assign these common macros to the register offsets for OPP_NOM by default for all voltage domains. These common macros can then be redefined properly to point to the OPP specific efuse register offset based on the desired OPP to program a specific voltage domain. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: DRA7: Update/Correct MPU and CORE OPP_NOM voltage valuesAnna, Suman2016-06-021-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current OPP_NOM voltage values defined for the MPU and CORE voltage domains are based on the initial DRA75x_74x_SR1.1_DM data manual. As per this DM, the PMIC boot voltage can be set to either 1.10V or 1.15V for VD_MPU, and either 1.06V or 1.15V for VD_CORE. While the current values are correct, the latter set of values are the values that are common across all DRA75x, DRA72x SoCs and for all current Silicon revisions. So, update both the MPU and CORE OPP_NOM voltages to 1.15V. The macros are also slightly reorganized so that both the MPU and CORE voltage domain values are defined together. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | dra7xx: Enable USB_PHY3 32KHz clockRoger Quadros2016-06-021-0/+1
| | | | | | | | | | | | | | | | | | | | | DRA7xx has a 32KHz PHY clock for USB_PHY3 that must be enabled for USB1 instance in Super-Speed. Signed-off-by: Roger Quadros <rogerq@ti.com>
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