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| author | Anna, Suman <s-anna@ti.com> | 2016-05-23 13:32:16 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-06-02 21:42:17 -0400 |
| commit | e42523f54434119609744a62dcc9173b3a50dc29 (patch) | |
| tree | 815372d3028fdf83a3cb13d98abb37bfe81a3d71 /arch/arm/include | |
| parent | 27c9596f680ecea01beb52181da72b7d7fab0d8c (diff) | |
| download | talos-obmc-uboot-e42523f54434119609744a62dcc9173b3a50dc29.tar.gz talos-obmc-uboot-e42523f54434119609744a62dcc9173b3a50dc29.zip | |
ARM: DRA7: Consolidate voltage macros across different SoCs
The voltage values for each voltage domain at an OPP is identical
across all the SoCs in the DRA7 family. The current code defines
one set of macros for DRA75x/DRA74x SoCs and another set for DRA72x
macros. Consolidate both these sets into a single set.
This is done so as to minimize the number of macros used when voltage
values will be added for other OPPs as well.
Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-omap5/clock.h | 19 |
1 files changed, 6 insertions, 13 deletions
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index a850043c89..8c121d6aa5 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -239,19 +239,12 @@ #define VDD_MPU_ES2_LOW 880 #define VDD_MM_ES2_LOW 880 -/* DRA74x/75x voltage settings in mv for OPP_NOM per DM */ -#define VDD_MPU_DRA752 1150 -#define VDD_CORE_DRA752 1150 -#define VDD_EVE_DRA752 1060 -#define VDD_GPU_DRA752 1060 -#define VDD_IVA_DRA752 1060 - -/* DRA72x voltage settings in mv for OPP_NOM per DM */ -#define VDD_MPU_DRA72x 1150 -#define VDD_CORE_DRA72x 1150 -#define VDD_EVE_DRA72x 1060 -#define VDD_GPU_DRA72x 1060 -#define VDD_IVA_DRA72x 1060 +/* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */ +#define VDD_MPU_DRA7 1150 +#define VDD_CORE_DRA7 1150 +#define VDD_EVE_DRA7 1060 +#define VDD_GPU_DRA7 1060 +#define VDD_IVA_DRA7 1060 /* Efuse register offsets for DRA7xx platform */ #define DRA752_EFUSE_BASE 0x4A002000 |
