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path: root/src/import/chips/p9/procedures/hwp/perv
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* PLL configuration updates -- permit e2e bypass executionJoe McGill2016-09-042-63/+125
* FAPI2 - Enable register ffdc supportRichard J. Knight2016-08-251-1/+0
* Fix PIR read/write flag in SPR map.LiuYangFan2016-08-241-1/+1
* Fix special case registers to be per-thread. Remove RMOR.Nick Klazynski2016-08-241-5/+4
* Fix spr map compile issue on X86/AIX.LiuYangFan2016-08-191-0/+2
* Fapi delay updatesAnusha Reddy Rangareddygari2016-08-121-4/+5
* Update prologs of mirrored files to apache licenseStephen Cprek2016-08-0569-552/+966
* FAPI_INF entering and exiting message updatesAnusha Reddy Rangareddygari2016-08-044-24/+24
* scan HWP updatesJoe McGill2016-08-042-5/+43
* Update RAM procedures.LiuYangFan2016-08-0110-355/+830
* L2 RAM procedures.LiuYangFan2016-08-0121-0/+1875
* Level 2 Hwp for p9_start_cbsAnusha Reddy Rangareddygari2016-07-211-2/+30
* p9_mem_pll_initf -- restore sync mode check, remove duplicate error XMLJoe McGill2016-07-212-37/+51
* Level 2 HWP p9_mem_pll_initfSunil.Kumar2016-07-201-46/+33
* VBU IPL -- update sim PLL configurationJoe McGill2016-07-204-18/+83
* Ec_level attribute support for DD1 attributesAnusha Reddy Rangareddygari2016-07-032-1/+2
* Level 2 HWP for p9_sbe_common - Update as in IPL v183Soma BhanuTej2016-06-241-54/+30
* Level 2 HWP p9_getecidAbhishek Agarwal2016-06-211-9/+9
* Level 2 HWP p9_getecidAbhishek Agarwal2016-06-132-6/+68
* Level 1 HWP p9_getecidAbhishek Agarwal2016-06-103-0/+119
* Level 2 HWP for p9_set_fsi_gp_shadowAnusha Reddy Rangareddygari2016-06-102-108/+78
* p9_sim_model_boot -- UpdatesJoe McGill2016-06-091-31/+7
* level 2 HWP p9_mem_pll_resetSunil.Kumar2016-06-011-4/+50
* Level 1 HWP p9_mem_pll_resetSunil.Kumar2016-06-013-0/+121
* Level 2 HWP for p9_sbe_nest_startclocks,p9_sbe_startclock_chipletsAnusha Reddy Rangareddygari2016-06-012-0/+309
* Level 2 HWP for p9_set_fsi_gp_shadowAnusha Reddy Rangareddygari2016-06-012-44/+83
* p9_mem_startclocks -- skip clock start in sync_modeJoe McGill2016-05-191-15/+21
* Level 2 HWP for p9_setup_sbe_configAnusha Reddy Rangareddygari2016-05-191-1/+8
* Level 2 HWP for p9_sbe_attr_setup,p9_setup_sbe_configAnusha Reddy Rangareddygari2016-05-162-131/+194
* p9_set_fsi_gp_shadow - updates RC init valuesAnusha Reddy Rangareddygari2016-05-121-2/+2
* Procedure update for L2Sunil.Kumar2016-05-041-2/+2
* IPL optimized codesAnusha Reddy Rangareddygari2016-05-042-116/+105
* Level 2 HWP for p9_sbe_commonAnusha Reddy Rangareddygari2016-05-041-0/+14
* Level 2 HWP for p9_sbe_commonAnusha Reddy Rangareddygari2016-05-041-13/+54
* Makefile Infrastructure for SBE Level 2 HWPsSunil.Kumar2016-04-222-1/+21
* PERV SBE: Level 2 Module - p9_sbe_commonAbhishek Agarwal2016-04-222-0/+407
* Level 2 HWP p9_mem_pll_setup.CSunil.Kumar2016-04-211-5/+81
* Level 2 HWP p9_chiplet_enable_ridi.CSunil.Kumar2016-03-022-12/+61
* Level 2 HWP p9_mem_startclocksSunil.Kumar2016-02-263-15/+200
* p9_sbe_check_master_stop15 Level 2Greg Still2016-02-263-2/+68
* Level 2 hwp for p9_start_cbsAnusha Reddy Rangareddygari2016-02-262-8/+25
* Level 2 HWP for p9_set_fsi_gp_shadowAnusha Reddy Rangareddygari2016-02-253-21/+116
* Level 2 HWP p9_setup_sbe_configSunil.Kumar2016-02-253-29/+176
* L1 Rev istep 0.(6-8,11,13,14),1.1,2.(1-13,15,18-20,22,26,27,30,32,34) V2Abhishek Agarwal2016-02-254-0/+202
* Level 2 HWP for p9_start_cbsSoma BhanuTej2016-02-221-2/+2
* p9_sbe_check_master_stop15 Level 1Greg Still2016-02-193-0/+139
* HWP for p9_start_cbsAnusha Reddy Rangareddygari2016-02-191-1/+1
* Level 1 HWP for p9_chiplet_enable_ridiAnusha Reddy Rangareddygari2016-02-193-0/+117
* Level 1 HWP for p9_switch_cfsimAnusha Reddy Rangareddygari2016-02-193-0/+117
* Level 1 HWP p9_check_slave_sbe_seeprom_completeAnusha Reddy Rangareddygari2016-02-193-0/+120
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