VBU IPL -- update sim PLL configuration

  Adjust refclock/PLL configuration to drive all mesh clocks from PLLs
    non-IO/wafer configuration (nest PLL bucket #1) -- default for sc/sq/fc
    IO/system model configuration (nest PLL bucket #2) -- default for mc

  Regression framework updates
    Remove dependence on sim-only varosc/refclock HWPs
    Scan from HW image (ultimately need to move to SEEPROM)
    Add memory attribute HWPs missing from flow
    Handle real/broadside scan options

  HWP updates
    Scan PLL configuration from image
    Preserve clock mux attribute programming
    First crack at removing unneeded PLL buckets from images/TOR
    Add boot support for warm IPL

Change-Id: Ic7f27ab3dfdf258471d91618adc8eae4cadb2e42
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26938
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26939
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

4 files changed, 83 insertions, 18 deletions

diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_initf.C
index 8a78dc2dc..6f62b2aa2 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_initf.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_initf.C
@@ -7,7 +7,7 @@
 /*                                                                        */
 /* EKB Project                                                            */
 /*                                                                        */
-/* COPYRIGHT 2015                                                         */
+/* COPYRIGHT 2015,2016                                                    */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -25,7 +25,7 @@
 // *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
 // *HWP FW Owner        : Sunil Kumar <skumar8j@in.ibm.com>
 // *HWP Team            : Perv
-// *HWP Level           : 1
+// *HWP Level           : 2
 // *HWP Consumed by     : HB
 //------------------------------------------------------------------------------
 
@@ -35,12 +35,61 @@
 
 
 
-fapi2::ReturnCode p9_mem_pll_initf(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chiplet)
+fapi2::ReturnCode p9_mem_pll_initf(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
 {
-    FAPI_DBG("Entering ...");
+    FAPI_INF("Entering ...");
 
-    FAPI_DBG("Exiting ...");
+    uint8_t l_sync_mode;
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_sync_mode),
+             "Error from FAPI_ATTR_GET (ATTR_MC_SYNC_MODE)");
 
-    return fapi2::FAPI2_RC_SUCCESS;
+    if (l_sync_mode == 0)
+    {
+        FAPI_DBG("Re-scanning PLL ring to set final frequency");
 
+        for (auto l_mcbist_target : i_target_chip.getChildren<fapi2::TARGET_TYPE_MCBIST>(fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            uint64_t l_mss_freq;
+            RingID l_ring_id;
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_FREQ, l_mcbist_target, l_mss_freq),
+                     "Error from FAPI_ATTR_GET (ATTR_MSS_FREQ)");
+
+            switch (l_mss_freq)
+            {
+                case fapi2::ENUM_ATTR_MSS_FREQ_MT1866:
+                    l_ring_id = mc_pll_bndy_bucket_1;
+                    break;
+
+                case fapi2::ENUM_ATTR_MSS_FREQ_MT2133:
+                    l_ring_id = mc_pll_bndy_bucket_2;
+                    break;
+
+                case fapi2::ENUM_ATTR_MSS_FREQ_MT2400:
+                    l_ring_id = mc_pll_bndy_bucket_3;
+                    break;
+
+                case fapi2::ENUM_ATTR_MSS_FREQ_MT2666:
+                    l_ring_id = mc_pll_bndy_bucket_4;
+                    break;
+
+                default:
+                    FAPI_ASSERT(false,
+                                fapi2::P9_MEM_PLL_INITF_UNSUPPORTED_FREQ().
+                                set_TARGET(l_mcbist_target).
+                                set_MSS_FREQ(l_mss_freq),
+                                "Unsupported MSS_FREQ attribute value!");
+            }
+
+            FAPI_TRY(fapi2::putRing(l_mcbist_target, l_ring_id, fapi2::RING_MODE_SET_PULSE_NSL),
+                     "Error from putRing");
+        }
+    }
+    else
+    {
+        FAPI_DBG("Skipping PLL re-scan");
+    }
+
+fapi_try_exit:
+    FAPI_INF("Exiting ...");
+    return fapi2::current_err;
 }
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_initf.H
index 1a5a6edf9..bf95f7f41 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_initf.H
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_initf.H
@@ -7,7 +7,7 @@
 /*                                                                        */
 /* EKB Project                                                            */
 /*                                                                        */
-/* COPYRIGHT 2015                                                         */
+/* COPYRIGHT 2015,2016                                                    */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -25,7 +25,7 @@
 // *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
 // *HWP FW Owner        : Sunil Kumar <skumar8j@in.ibm.com>
 // *HWP Team            : Perv
-// *HWP Level           : 1
+// *HWP Level           : 2
 // *HWP Consumed by     : HB
 //------------------------------------------------------------------------------
 
@@ -49,7 +49,7 @@ typedef fapi2::ReturnCode (*p9_mem_pll_initf_FP_t)(const fapi2::Target<fapi2::TA
 /// @return  FAPI2_RC_SUCCESS if success, else error code.
 extern "C"
 {
-    fapi2::ReturnCode p9_mem_pll_initf(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chiplet);
+    fapi2::ReturnCode p9_mem_pll_initf(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
 }
 
 #endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_set_fsi_gp_shadow.C b/src/import/chips/p9/procedures/hwp/perv/p9_set_fsi_gp_shadow.C
index 17e748769..671aa7620 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_set_fsi_gp_shadow.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_set_fsi_gp_shadow.C
@@ -42,6 +42,7 @@ fapi2::ReturnCode p9_set_fsi_gp_shadow(const
                                        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
 {
     fapi2::buffer<uint8_t> l_read_attr;
+    fapi2::buffer<uint32_t> l_cfam_data;
     FAPI_INF("Entering ...");
 
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_FSI_GP_SHADOWS_OVERWRITE, i_target_chip,
@@ -77,13 +78,21 @@ fapi2::ReturnCode p9_set_fsi_gp_shadow(const
 
         //Setting ROOT_CTRL5_COPY register value
         //CFAM.ROOT_CTRL5_COPY = p9SetFsiGpShadow::ROOT_CTRL5_FLUSHVALUE
+        FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_ROOT_CTRL5_COPY_FSI,
+                                        l_cfam_data));
+        l_cfam_data = (l_cfam_data & p9SetFsiGpShadow::ROOT_CTRL5_MASK) |
+                      p9SetFsiGpShadow::ROOT_CTRL5_FLUSHVALUE;
         FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_ROOT_CTRL5_COPY_FSI,
-                                        p9SetFsiGpShadow::ROOT_CTRL5_FLUSHVALUE));
+                                        l_cfam_data));
 
         //Setting ROOT_CTRL6_COPY register value
         //CFAM.ROOT_CTRL6_COPY = p9SetFsiGpShadow::ROOT_CTRL6_FLUSHVALUE
+        FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_ROOT_CTRL6_COPY_FSI,
+                                        l_cfam_data));
+        l_cfam_data = (l_cfam_data & p9SetFsiGpShadow::ROOT_CTRL6_MASK) |
+                      p9SetFsiGpShadow::ROOT_CTRL6_FLUSHVALUE;
         FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_ROOT_CTRL6_COPY_FSI,
-                                        p9SetFsiGpShadow::ROOT_CTRL6_FLUSHVALUE));
+                                        l_cfam_data));
 
         //Setting ROOT_CTRL7_COPY register value
         //CFAM.ROOT_CTRL7_COPY = p9SetFsiGpShadow::ROOT_CTRL7_FLUSHVALUE
@@ -92,8 +101,12 @@ fapi2::ReturnCode p9_set_fsi_gp_shadow(const
 
         //Setting ROOT_CTRL8_COPY register value
         //CFAM.ROOT_CTRL8_COPY = p9SetFsiGpShadow::ROOT_CTRL8_FLUSHVALUE
+        FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_ROOT_CTRL8_COPY_FSI,
+                                        l_cfam_data));
+        l_cfam_data = (l_cfam_data & p9SetFsiGpShadow::ROOT_CTRL8_MASK) |
+                      p9SetFsiGpShadow::ROOT_CTRL8_FLUSHVALUE;
         FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_ROOT_CTRL8_COPY_FSI,
-                                        p9SetFsiGpShadow::ROOT_CTRL8_FLUSHVALUE));
+                                        l_cfam_data));
 
         //Setting PERV_CTRL0_COPY register value
         //CFAM.PERV_CTRL0_COPY = p9SetFsiGpShadow::PERV_CTRL0_FLUSHVALUE
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_set_fsi_gp_shadow.H b/src/import/chips/p9/procedures/hwp/perv/p9_set_fsi_gp_shadow.H
index ec19830ce..fd6bb3f0e 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_set_fsi_gp_shadow.H
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_set_fsi_gp_shadow.H
@@ -43,15 +43,18 @@ enum P9_SET_FSI_GP_SHADOW_Public_Constants
 {
     PERV_CTRL0_FLUSHVALUE = 0x7C0E2000,
     PERV_CTRL1_FLUSHVALUE = 0x63C00000,
+    ROOT_CTRL0_FLUSHVALUE = 0x80FF4003,
     ROOT_CTRL1_FLUSHVALUE = 0x00180000,
     ROOT_CTRL2_FLUSHVALUE = 0x0000E000,
-    ROOT_CTRL7_FLUSHVALUE = 0x0,
-    ROOT_CTRL8_FLUSHVALUE = 0xEEECF300,
-    ROOT_CTRL0_FLUSHVALUE = 0x80FF4003,
+    ROOT_CTRL5_FLUSHVALUE = 0x00000000,
     ROOT_CTRL3_FLUSHVALUE = 0x0080C000,
-    ROOT_CTRL4_FLUSHVALUE = 0x0,
-    ROOT_CTRL5_FLUSHVALUE = 0x0,
-    ROOT_CTRL6_FLUSHVALUE = 0x00800000
+    ROOT_CTRL4_FLUSHVALUE = 0x00000000,
+    ROOT_CTRL5_MASK       = 0xFFFF0000,
+    ROOT_CTRL6_FLUSHVALUE = 0x00800000,
+    ROOT_CTRL6_MASK       = 0xF0000000,
+    ROOT_CTRL7_FLUSHVALUE = 0x00000000,
+    ROOT_CTRL8_FLUSHVALUE = 0xEEECF300,
+    ROOT_CTRL8_MASK       = 0x0000008F
 };
 }