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authorJoe McGill <jmcgill@us.ibm.com>2016-07-19 13:52:14 -0500
committerDaniel M. Crowell <dcrowell@us.ibm.com>2016-07-21 11:15:53 -0400
commitdb2f55ed0d57b058adf78bcb45ce22c1aa57c6fc (patch)
treef04a14cfbf21844a26484c4c84ddfaa1c9c88ac1 /src/import/chips/p9/procedures/hwp/perv
parent8232138485eaf9636177ccab4f28ec4fb28db081 (diff)
downloadtalos-hostboot-db2f55ed0d57b058adf78bcb45ce22c1aa57c6fc.tar.gz
talos-hostboot-db2f55ed0d57b058adf78bcb45ce22c1aa57c6fc.zip
p9_mem_pll_initf -- restore sync mode check, remove duplicate error XML
Change-Id: Ia3491b1c609ed6e8f680133d53b27884e6f8da29 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27239 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com> Reviewed-by: Brian R. Silver <bsilver@us.ibm.com> Dev-Ready: Brent Wieman <bwieman@us.ibm.com> Reviewed-by: Brent Wieman <bwieman@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27247 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/perv')
-rw-r--r--src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_initf.C86
-rw-r--r--src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_initf.H2
2 files changed, 51 insertions, 37 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_initf.C
index 064d098cd..ea1cee8db 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_initf.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_initf.C
@@ -33,50 +33,64 @@
//## auto_generated
#include "p9_mem_pll_initf.H"
-fapi2::ReturnCode p9_mem_pll_initf(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chiplet)
+
+
+fapi2::ReturnCode p9_mem_pll_initf(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
{
- uint64_t l_read_attr = 0;
- RingID ringID = mc_pll_bndy_bucket_1;
- FAPI_INF("Entering p9_mem_pll_initf ...");
+ FAPI_INF("Entering ...");
- for (auto l_trgt_chplt : i_target_chiplet.getChildren<fapi2::TARGET_TYPE_MCBIST>
- (fapi2::TARGET_STATE_FUNCTIONAL))
+ uint8_t l_sync_mode;
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_sync_mode),
+ "Error from FAPI_ATTR_GET (ATTR_MC_SYNC_MODE)");
+
+ if (l_sync_mode == 0)
{
- FAPI_INF("get the attribute ATTR_MSS_FREQ");
- FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_FREQ, l_trgt_chplt, l_read_attr));
+ FAPI_DBG("Re-scanning PLL ring to set final frequency");
- switch(l_read_attr)
+ for (auto l_mcbist_target : i_target_chip.getChildren<fapi2::TARGET_TYPE_MCBIST>(fapi2::TARGET_STATE_FUNCTIONAL))
{
- case fapi2::ENUM_ATTR_MSS_FREQ_MT1866:
- ringID = mc_pll_bndy_bucket_1;
- break;
-
- case fapi2::ENUM_ATTR_MSS_FREQ_MT2133:
- ringID = mc_pll_bndy_bucket_2;
- break;
-
- case fapi2::ENUM_ATTR_MSS_FREQ_MT2400:
- ringID = mc_pll_bndy_bucket_3;
- break;
-
- case fapi2::ENUM_ATTR_MSS_FREQ_MT2666:
- ringID = mc_pll_bndy_bucket_4;
- break;
-
- default:
- FAPI_ASSERT(false,
- fapi2::MSS_FREQ_VALUE_NOT_VALID()
- .set_MSS_FREQ(l_read_attr)
- .set_MCBIST_TARGET(l_trgt_chplt),
- "Invalid value of ATTR_MSS_FREQ");
- }
+ uint64_t l_mss_freq = 0;
+ RingID l_ring_id = mc_pll_bndy_bucket_1;
- FAPI_TRY(fapi2::putRing(l_trgt_chplt, ringID, fapi2::RING_MODE_SET_PULSE_NSL));
- }
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_FREQ, l_mcbist_target, l_mss_freq),
+ "Error from FAPI_ATTR_GET (ATTR_MSS_FREQ)");
+
+ switch (l_mss_freq)
+ {
+ case fapi2::ENUM_ATTR_MSS_FREQ_MT1866:
+ l_ring_id = mc_pll_bndy_bucket_1;
+ break;
+
+ case fapi2::ENUM_ATTR_MSS_FREQ_MT2133:
+ l_ring_id = mc_pll_bndy_bucket_2;
+ break;
+
+ case fapi2::ENUM_ATTR_MSS_FREQ_MT2400:
+ l_ring_id = mc_pll_bndy_bucket_3;
+ break;
- FAPI_INF("Exiting p9_mem_pll_initf ...");
+ case fapi2::ENUM_ATTR_MSS_FREQ_MT2666:
+ l_ring_id = mc_pll_bndy_bucket_4;
+ break;
+
+ default:
+ FAPI_ASSERT(false,
+ fapi2::P9_MEM_PLL_INITF_UNSUPPORTED_FREQ().
+ set_TARGET(l_mcbist_target).
+ set_MSS_FREQ(l_mss_freq),
+ "Unsupported MSS_FREQ attribute value!");
+ }
+
+ FAPI_TRY(fapi2::putRing(l_mcbist_target, l_ring_id, fapi2::RING_MODE_SET_PULSE_NSL),
+ "Error from putRing");
+ }
+ }
+ else
+ {
+ FAPI_DBG("Skipping PLL re-scan");
+ }
fapi_try_exit:
+ FAPI_INF("Exiting ...");
return fapi2::current_err;
}
-
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_initf.H
index bf95f7f41..be9725c57 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_initf.H
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_initf.H
@@ -45,7 +45,7 @@ typedef fapi2::ReturnCode (*p9_mem_pll_initf_FP_t)(const fapi2::Target<fapi2::TA
/// Request SBE to scan said ring and data stored as a ring image.
///
///
-/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PROC_CHIP target
+/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target
/// @return FAPI2_RC_SUCCESS if success, else error code.
extern "C"
{
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