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path: root/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C
Commit message (Expand)AuthorAgeFilesLines
* Updates error paths for PRD FIR checkingStephen Glancy2017-10-021-1/+1
* L3 work for mss xmlsJacob Harvey2017-08-181-2/+2
* L3 draminit and mss_libJacob Harvey2017-07-261-5/+4
* Turn off A17 if not neededJacob Harvey2017-06-251-0/+59
* Double POR timings (tMOD, tMRD, and tZQ) for more margin per labAndre Marin2017-06-141-7/+11
* Remove ZQCAL redundant CCS inst, move to draminit_trainingAndre Marin2017-05-251-50/+4
* Disable RTT_WR during WR_LEVEL cal step, and set equivalent terminationsLouis Stermole2017-03-151-1/+175
* Add BCW API for rank presence, buffer training, mrep timing and UTs.Andre Marin2017-01-031-12/+3
* Add common functionality between RCD and data buffer control word APIAndre Marin2016-12-071-3/+3
* Add a common MRS engine to set up CCS instructions and UTs.Andre Marin2016-12-061-33/+22
* Add DDR4 data buffer control words (BCWs) infrastructure & UT's.Andre Marin2016-12-061-0/+21
* Add register API for PHY Rank Pair registersLouis Stermole2016-09-201-1/+1
* Changes related to PHY register reviewBrian Silver2016-09-031-18/+14
* Add ZQCL instruction after MRS have completedBrian Silver2016-09-021-2/+42
* Create MRS data structuresBrian Silver2016-09-021-49/+9
* Add ZQCL instruction after MRS have completedBrian Silver2016-08-241-2/+42
* Create MRS data structuresBrian Silver2016-08-071-0/+125
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