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author | Andre Marin <aamarin@us.ibm.com> | 2016-11-24 11:01:12 -0600 |
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committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2016-12-06 10:34:28 -0500 |
commit | ff34b02d569f9c45bcb5a3832fdcd7f12ef07519 (patch) | |
tree | ae1a5e5daa1d0e54c3591a61166ac9a34a921d56 /src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C | |
parent | 01eb02a8ba7730945d5eb785ef7cf1ff2b59def9 (diff) | |
download | talos-hostboot-ff34b02d569f9c45bcb5a3832fdcd7f12ef07519.tar.gz talos-hostboot-ff34b02d569f9c45bcb5a3832fdcd7f12ef07519.zip |
Add a common MRS engine to set up CCS instructions and UTs.
Cascade MRS engine to common copy-pasted code to
mrs_load, latch_wr_vref and mrs_one_shot.
Change-Id: Iabd7848816a43d012bed4f403504985488fe332c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33010
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33026
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C | 55 |
1 files changed, 22 insertions, 33 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C index 2017cc1d5..67349352a 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C @@ -48,13 +48,33 @@ using fapi2::FAPI2_RC_SUCCESS; namespace mss { +/// +/// @brief Sets up MRS CCS instructions +/// @param[in] i_target a fapi2::Target DIMM +/// @param[in] i_data the completed MRS data to send +/// @param[in] i_rank the rank to send to +/// @param[in,out] io_inst a vector of CCS instructions we should add to +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< > +fapi2::ReturnCode mrs_engine( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const mrs_data<fapi2::TARGET_TYPE_MCBIST>& i_data, + const uint64_t i_rank, + std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst ) +{ + FAPI_TRY( mrs_engine(i_target, i_data, i_rank, i_data.iv_delay, io_inst) ); + +fapi_try_exit: + return fapi2::current_err; +} + namespace ddr4 { /// /// @brief Perform the mrs_load DDR4 operations - TARGET_TYPE_DIMM specialization /// @param[in] i_target a fapi2::Target<TARGET_TYPE_DIMM> -/// @param[in] io_inst a vector of CCS instructions we should add to +/// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// fapi2::ReturnCode mrs_load( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, @@ -89,38 +109,7 @@ fapi2::ReturnCode mrs_load( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, { for (const auto& r : l_ranks) { - // Note: this isn't general - assumes Nimbus via MCBIST instruction here BRS - ccs::instruction_t<TARGET_TYPE_MCBIST> l_inst_a_side = - ccs::mrs_command<TARGET_TYPE_MCBIST>(i_target, r, d.iv_mrs); - ccs::instruction_t<TARGET_TYPE_MCBIST> l_inst_b_side; - - // Thou shalt send 2 MRS, one for the a-side and the other inverted for the b-side. - // If we're on an odd-rank then we need to mirror - // So configure the A-side, mirror if necessary and invert for the B-side - FAPI_TRY( d.iv_func(i_target, l_inst_a_side, r) ); - - FAPI_TRY( mss::address_mirror(i_target, r, l_inst_a_side) ); - l_inst_b_side = mss::address_invert(l_inst_a_side); - - // Not sure if we can get tricky here and only delay after the b-side MR. The question is whether the delay - // is needed/assumed by the register or is purely a DRAM mandated delay. We know we can't go wrong having - // both delays but if we can ever confirm that we only need one we can fix this. BRS - l_inst_a_side.arr1.insertFromRight<MCBIST_CCS_INST_ARR1_00_IDLES, - MCBIST_CCS_INST_ARR1_00_IDLES_LEN>(d.iv_delay); - l_inst_b_side.arr1.insertFromRight<MCBIST_CCS_INST_ARR1_00_IDLES, - MCBIST_CCS_INST_ARR1_00_IDLES_LEN>(d.iv_delay); - - // Dump out the 'decoded' MRS and trace the CCS instructions. - FAPI_TRY( d.iv_dumper(l_inst_a_side, r) ); - - FAPI_INF("MRS%02d (%d) 0x%016llx:0x%016llx %s:rank %d a-side", uint8_t(d.iv_mrs), d.iv_delay, - l_inst_a_side.arr0, l_inst_a_side.arr1, mss::c_str(i_target), r); - FAPI_INF("MRS%02d (%d) 0x%016llx:0x%016llx %s:rank %d b-side", uint8_t(d.iv_mrs), d.iv_delay, - l_inst_b_side.arr0, l_inst_b_side.arr1, mss::c_str(i_target), r); - - // Add both to the CCS program - io_inst.push_back(l_inst_a_side); - io_inst.push_back(l_inst_b_side); + FAPI_TRY( mrs_engine(i_target, d, r, io_inst) ); } } |