diff options
| author | Jacob Harvey <jlharvey@us.ibm.com> | 2017-07-13 15:06:13 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-07-26 10:29:10 -0400 |
| commit | fd029f5afa54473a055a9b938d53da2e556b5a75 (patch) | |
| tree | 87215911f0c9d138c74abe760334dd20a5864856 /src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C | |
| parent | 135d297bcee4f80451c3fd5e4061f1010fe4f6d6 (diff) | |
| download | talos-hostboot-fd029f5afa54473a055a9b938d53da2e556b5a75.tar.gz talos-hostboot-fd029f5afa54473a055a9b938d53da2e556b5a75.zip | |
L3 draminit and mss_lib
Change-Id: If5cae63291864da0b87d6a1e82407da9358d62d2
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43121
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43278
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C index 22bd97ff7..a9196951b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C @@ -27,7 +27,7 @@ /// @file mrs_load_ddr4.C /// @brief Run and manage the DDR4 mrs loading /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 @@ -110,6 +110,8 @@ fapi2::ReturnCode is_a17_needed(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_t // Set this to good in case no dimms and we're running unit tests fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; + o_is_needed = false; + // Loop over the DIMMs and see if A17 is needed for one of them // If so, we enable the parity bit in the PHY for (const auto& l_dimm : mss::find_targets<TARGET_TYPE_DIMM>(i_target) ) @@ -119,10 +121,7 @@ fapi2::ReturnCode is_a17_needed(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_t bool l_temp = false; FAPI_TRY( is_a17_needed( l_dimm, l_temp), "%s Failed to get a17 boolean", mss::c_str(l_dimm) ); - if (l_temp == true) - { - o_is_needed = true; - } + o_is_needed = o_is_needed | l_temp; } fapi_try_exit: |
