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| author | Andre Marin <aamarin@us.ibm.com> | 2016-12-15 11:04:42 -0600 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2017-01-03 21:37:40 -0500 |
| commit | 57bcb1f7cc08311036ddedcebfa788b7947cc59b (patch) | |
| tree | 87e55117854db2204e492dfc21af71a635fb757f /src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C | |
| parent | 2ed96daee929460c101fbd1051045502268c66e2 (diff) | |
| download | talos-hostboot-57bcb1f7cc08311036ddedcebfa788b7947cc59b.tar.gz talos-hostboot-57bcb1f7cc08311036ddedcebfa788b7947cc59b.zip | |
Add BCW API for rank presence, buffer training, mrep timing and UTs.
Change-Id: I9346c280ba95d792b6fb7d1047a6a25ea8ea66ba
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33959
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33978
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C | 15 |
1 files changed, 3 insertions, 12 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C index a3e4542b5..7f42d97d6 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C @@ -37,7 +37,8 @@ #include <mss.H> #include <lib/dimm/ddr4/mrs_load_ddr4.H> -#include <lib/dimm/bcw_load.H> +#include <lib/dimm/ddr4/control_word_ddr4.H> +#include <lib/dimm/ddr4/data_buffer_ddr4.H> #include <lib/eff_config/timing.H> using fapi2::TARGET_TYPE_MCBIST; @@ -150,17 +151,7 @@ fapi2::ReturnCode mrs_load( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, if( l_dimm_type == fapi2::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { - constexpr uint8_t FSPACE = 0; - constexpr uint8_t WORD = 6; - - // From the DDR4DB02 Spec: BC06 - Command Space Control Word - // After issuing a data buffer command via writes to BC06 waiting for tMRC(16 tCK) - // is required before the next DRAM command or BCW write can be issued. - FAPI_TRY( function_space_select<0>(i_target, io_inst) ); - - FAPI_TRY( control_word_engine<BCW_8BIT>(i_target, - cw_data(FSPACE, WORD, eff_dimm_ddr4_bc06, mss::tmrc()), - io_inst) ); + FAPI_TRY( set_command_space(i_target, command::ZQCL, io_inst) ); } fapi_try_exit: |
