| Commit message (Collapse) | Author | Age | Files | Lines |
... | |
|
|
|
|
|
|
|
|
|
| |
Task 43959
Change-Id: I6990f8c35a17da764c5905a3fd4ebba9183571a3
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1773
Tested-by: Jenkins Server
Reviewed-by: Van H. Lee <vanlee@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
- S1 only has xbus1
Change-Id: Ieb9c64302866f6f3457e7174bf509f50a39034f8
RTC: 47150
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1708
Tested-by: Jenkins Server
Reviewed-by: CAMVAN T. NGUYEN <ctnguyen@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
When executing the nap instruction, all thread state can be
lost. This was causing r0 to be lost, which contained the
system-call number for the idle thread to request permission
to execute nap and as a result 'task-yield' was executed
instead of 'cpu-nap' after the idle thread took its first
nap.
Re-arranged the sreset code that handles nap-wakeup to deal
with thread-state being lost when entering nap and instead
using the previously saved task-state from the 'cpu-nap'
system call.
Change-Id: Id7468a8577c4d7b273b23bc97e7dd040555e7b67
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1567
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
| |
Change-Id: I1b441f0714af1a9579b1e003b70952efe29a5523
RTC: 44947
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1551
Tested-by: Jenkins Server
Reviewed-by: MIKE J. JONES <mjjones@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Updating pnor build process in the following ways:
-Murano/Venice/Tuleta pnor images now build in ODE sandbox
-They are built using the ffs tool
-hbDistribute delivers necessary files to ODE to
enable building in ODE sandbox.
-Delivering ffs_hb.H to CMVC to enable commonality
of FFS user data with Hardware Server
-Disabled failing Scom test case assoicated with new
bbuild. Opened Issue to track resolution.
Note, VBU image is still built the old way. That will be
updated next sprint.
Change-Id: Ie4cdca053c3f4221e5ca051a68157159970dfce2
RTC: 35045
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1436
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
| |
RTC: 44730
Change-Id: Ifaeecc659e1bfd8ded4744dc591fc993471519ba
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1471
Tested-by: Jenkins Server
Reviewed-by: Mark W. Wenning <wenning@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Moving to driver b0729a meant a previous p8.act.patch was
no longer neaded. Completing the cleanup by completely removing
the file from git now.
Change-Id: I0218a958de26abc359fdc8b506bde8559e40abd0
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1408
Tested-by: Jenkins Server
Reviewed-by: Mark W. Wenning <wenning@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The previous Backing build pointed to by bbuild was deleted so
I am moving to a more recent one.
I also removed a couple workarounds from workarounds that don't
seem to be needed anymore.
Change-Id: I7c6ce8233810853b52d82648a89f84130dd683cc
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1406
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
| |
RTC: 42296
Change-Id: I9f470f9e41c22ed28bd0365aec23b91414258945
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1235
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Reviewed-by: Mark W. Wenning <wenning@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
| |
Uses the scom from proc_thread_control HWP to start all of the
threads that aren't started yet on the master core.
Change-Id: I93efba6ebebbf9d286a399fc58fa437b30e830b1
RTC: 37008
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1242
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
When enabling LPC2SPI in Venice I had to override a setting
in the P8_VENICE.config file to enable the LPC2SPI FPGA.
That setting is now changed in the FSP Backing builds,
so the override is no longer needed.
RTC:43661
Change-Id: Ieba9956eb13d43f866a021cd77fc5c4360202920
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1279
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
See SW149779. The PHYP simics model is changing the location of
phys_mem to be under system_cmp0 and renaming venice_cec_chip_cmp0
to proc_venicechip_cmp0. Change our debug and startup scripts
to match these new naming conventions.
Change-Id: I32b2ff8fa3467806ac4d7fac1b8b2e1db0796259
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1256
Tested-by: Jenkins Server
Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Mark W. Wenning <wenning@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Switch to use manual PNOR images in simics
Provided method for VPO to override
Change-Id: I18195b645053f1ce90b4322ae2e09b6b08844331
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1241
Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Jenkins Server
|
|
|
|
|
|
|
|
|
| |
Change-Id: I94c4d5d378f3c4f615e33af3bed6a04e4c55c145
RTC: 42625
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1203
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
| |
Change-Id: I8f7e5e3a85dd8ffc39b1970cd78ed2c925608d3d
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1205
Tested-by: Jenkins Server
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Replaced 'cpfiles' with a set of makefiles that does all
of the old function and also allows more complex behaviors
such as creating a TAR file of all our common code.
Moved the delivery location of our content into a simics sandbox
to match the locations in an FSP build. Updated debug tools
to handle living in a different location.
Removed 'post_model_hook.simics' and replaced with the
{startup,standalone,combined}.simics files.
Updated various scripts that were calling 'cpfiles' to instead
call 'hbDistribute' (which in turn calls the makefiles).
RTC: 41640
Change-Id: I10d1782ae89a397725e880c44ba44d01b0e4b011
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1173
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
| |
Change-Id: I85c526dcbea8106ca4dda68e56e622f649cdfdd6
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1178
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
| |
Change-Id: I19e5c373713b6e8b12386266c5c2c3a015068d5a
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1132
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Tweaked our various scripts to put the hostboot images in
$sb/../images/ppc/lab/flash as that is where simics
looks for them now.
Change-Id: I3b019a460a6f5f03ad666d93724ec1d6fe1ff3c9
RTC: 35728
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1095
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Updating the Simics level to get FSI fixes to allow multiple
chips to work. This also allows us to remove some previous
workarounds.
The new Simics build pulled in a different PNOR so needed to
disable some of the tests.
The new Simics build also modified some of the L3 objects so
changes were required to some debug tools.
Had to update the VENICE config since Ched rewired it to look
like MURANO/Tuleta.
Testing:
Verified 2-proc, 4-centaur MURANO config
Verified 2-proc, 4-centaur VENICE config
Change-Id: I6aaaf8aad2f82dbfffb8ade551d545bedaa3e048
RTC: 41305
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1066
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
| |
Change-Id: Icab145ce932ff77e8a84e6bdf58709b04feb5c37
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/976
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Moving up levels to get to a stable fips810 driver that
includes some Simics fixes
RTC: 40995
Change-Id: Iedbefc0f765b51d18af5a106fb4db89a9531f739
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/946
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
| |
RTC: 39856
Change-Id: I3fd6427955d84451ada80791b4fad14c061951d5
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/873
Tested-by: Jenkins Server
Reviewed-by: Brian H. Horton <brianh@linux.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Change hwas code that reads and stores chip ID and EC Level from the method
that had different actions based on master processor versus everything else.
Add a cause_effect action to correctly populate the SCOM register 0x000f000f
from the simics LOGIC 0xff000009 register on a read.
Task 40101 will remove these action files once FIPS is updated.
Change-Id: Iaba30f0e52a24807fb5c658518e891b47f0f96c5
RTC: 40097
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/832
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Changed the citest script to read g_ModulesCompleted before
g_ModulesStarted. Otherwise, g_ModulesStarted value can
be stale relative to the g_ModulesCompleted, so they appear
to have the same value which is the indication that the test
cases have completed. Instead read g_ModulesCompleted first,
which will be smaller than g_ModulesStarted unless we really
are complete.
Change-Id: Ifeaf7cefbcfe481fab41804308af0e7c5dccf293
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/898
Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: Mark W. Wenning <wenning@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
| |
Choosing the latest 1213.810 build for now, pending a response
from Charlie about what driver we can rely on sticking around.
Change-Id: I38ba7e8b0e3bff43ec882ab05c68413424a6dcb0
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/882
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
| |
RTC: 35323
Change-Id: Ifd626870fcc31f94a684f8a19fdc7816e092a7fa
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/798
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
. remove hwas functions in istep 4.*
. add new hwas functions to istep 6.* as per 0.99 ipl flow
. split hwas into common and platform specific layers for hostboot/fsp sharing
. add presence detect logic
. add chip id/ec logic, including ATTR_CHIP_ID (Story 35542)
Change-Id: I436fe54b1a7f7547cbc9e19beda2d47105c11871
RTC: 35777
RTC: 35542
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/800
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
We need to temporarily disable multiple Centaurs in our config
until the Simics models work again. Right now they get FSI
errors.
Change-Id: Ia963ad7e8c90664bfa7d70b8aa2c963d634bbf06
RTC: 39901
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/820
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Tested-by: Jenkins Server
|
|
|
|
|
|
|
|
|
|
|
| |
new bbuild will be b0330a_1213.810
RTC: 38362
Change-Id: I4ee508d8a77efea8b49f013ea207e64c8362786c
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/789
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Task 38013
Latest bbuild has the updates for the buildIndScom.pl so we can
remove the patches.
I also deleted the p8_pnor.act patch that I forgot earlier
Change-Id: Ibcc8c79cb82590b9110eeaf91e8f5d9bed5fa934
RTC: 36813
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/814
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
| |
The previous bbuild got deleted.
Change-Id: I6a6970a43ff09c8777f0f1870325306e05907d79
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/803
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This is work for Task 38048
-Updated bbuild to an 810 build with the latest Simics support
-Pulled support for Salerno from build tools
-Changed DEFAULT_MACHINE to MURANO
-Updated testcases to follow error logging guidelines
-Fixed up some FSI error handling bugs
-Disabled FSI loopback on VENICE (fix with Task 39187)
-Disabled a few testcases (see Impediment 39188)
Verified both MURANO and VENICE configurations
Change-Id: Ie7761f49c9e653489c8c4dad261b1c8852fa7548
RTC: 35596
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/791
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
| |
Also added a patch for the action files so that I
can allow the testcases to run.
Change-Id: I86e39b5b8efd31ba8ea3b037470f88be68ec5818
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/702
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
| |
RTC: 38206
Change-Id: Iab79041931db533ad6b6ebd057c1ef9fe4c4b8cc
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/714
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
| |
Update bbuild to released 1209 driver (b0229a_1209.760)
RTC: 35596
Change-Id: Ifeb06070ac61943982509e88df6a1ca27c5e0aea
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/717
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
| |
Change-Id: Iccbb08baa7d1f691fac73ea71fee7d3b2d87f1ad
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/716
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This includes a hack to allow access to our fake PNOR data via
the ECCB scom registers. This hack will be removed once Simics
provides a real ECCB model.
Changes to INTR testcase were needed due to bugs exposed by the
timing changes when enabling this new code.
Note that the default operating mode will remain LPC_MEM because
the current version of the ECCB model causes the IPL to take
close to 10 minutes to complete.
Change-Id: Icc236bffd52ba8214ec920f9a496adec138e54d9
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/692
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
|
|
|
|
|
|
|
| |
Change-Id: I1d4e31c171eb692e3604ddb40bc2ad9b0636ce1d
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/656
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
-Updated bbuild to c0131a_1205.760 (released 1205.760 driver)
-Removed writes to MCRSP32 regs from testcase (see Issue 35803)
-Removed access to made-up reg 0x12345 from scom test
-Removed Simics workaround for reg 0x02011403 in scom test
-Updated debug FFDC for FSI errors
Change-Id: I2714d3b179406d35f7e460a6c0629c961083e6df
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/647
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
| |
Change-Id: Iff47274d72c3994923234c998894671db6e833ba
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/632
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
| |
RTC Impediment 4656
A Simics-side change is going into fips under 821496
Change-Id: I76984bf8c4906334875e9738ab992cc6a1933ec6
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/617
Tested-by: Jenkins Server
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
|
|
|
|
|
|
|
|
| |
Change-Id: If6b499d819b71298b8a64e096e1eb83c639ad645
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/517
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
build to b1129a_1149.760. I also fixed up a bug in the scom
testcase that was seen in some configs.
Verified against SALERNO, VENICE and VENICE 2-chip models.
Change-Id: I5c6c71a1c8f782b4d1a9c0f13faa9dc2ded4d911
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/521
Tested-by: Jenkins Server
Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
|
|
| |
Change-Id: Ie9f6963070ced0a39c2e62f685c79d6da01fdcdb
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/488
Tested-by: Jenkins Server
Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com>
Reviewed-by: Monte K. Copeland <copelanm@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
|
|
|
|
|
|
|
| |
Change-Id: I2eaef856d94a4d84db729e1f9d1e9b5b0f8d0845
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/496
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
| |
Also turned off the FSI init in the FSI and SCOM testcases because
it is now called by the istep code automatically.
Updated the centuar.chip file to add scom registers.
Change-Id: Icf1278808eeb67c1afdabf02b0ad08bc99c8ed40
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/477
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
|
|
|
|
|
|
|
| |
Change-Id: I98f57582b9ba82d3b2d6f0717e0ca8811172efcc
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/475
Tested-by: Jenkins Server
Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
RTC Story 3792
- Added 7 more Venice targets and 7 more Centaur targets to the
simics_VENICE.system.xml to match the latest simics config
Note: remove Centaurs are currently disabled due to SW107421
- Modified testcases to be more tolerant of system config differences
- Changes to initialization flow to be more tolerant of missing
chips
- Expanded the size of the HB_DATA section of PNOR to hold the
additional targets (up to 128KB space now, actual is 36KB)
Change-Id: Ic92708ccb147fb18bf992ef3ac318a287d32fafe
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/445
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
|
|
|
|
|
|
|
|
| |
Change-Id: I88bf5ce464cdeceb3e151bde72fb51295ede07c0
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/428
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Reviewed-by: Terry J. Opie <opiet@us.ibm.com>
|