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| author | Dan Crowell <dcrowell@us.ibm.com> | 2011-11-02 10:48:20 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2011-11-02 17:01:49 -0500 |
| commit | 849c586994dedbc8b5707997825de249e6843b5d (patch) | |
| tree | 411eec4b0585d5a3bb89d007e3987b2a0d89a443 /src/build/citest | |
| parent | a0c271b82e8656c425bbe62c70a32e7af3e9cce9 (diff) | |
| download | talos-hostboot-849c586994dedbc8b5707997825de249e6843b5d.tar.gz talos-hostboot-849c586994dedbc8b5707997825de249e6843b5d.zip | |
Adding test to scom a centaur chip.
Also turned off the FSI init in the FSI and SCOM testcases because
it is now called by the istep code automatically.
Updated the centuar.chip file to add scom registers.
Change-Id: Icf1278808eeb67c1afdabf02b0ad08bc99c8ed40
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/477
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/build/citest')
| -rwxr-xr-x | src/build/citest/etc/workarounds.presimsetup | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/src/build/citest/etc/workarounds.presimsetup b/src/build/citest/etc/workarounds.presimsetup index c93cbf311..4dd47b267 100755 --- a/src/build/citest/etc/workarounds.presimsetup +++ b/src/build/citest/etc/workarounds.presimsetup @@ -41,11 +41,22 @@ sed -i -e's/SETENV GFW_P8_VENICE_L3_MB_SIZE.*/SETENV GFW_P8_VENICE_L3_MB_SIZE 8/ # Backing build already contains 910431. Leave this workaround here for future scomdef files #sed -i -e's/SETENV GFW_P8_VENICE_MODEL_EC.*/SETENV GFW_P8_VENICE_MODEL_EC 910431/' $sb/simu/configs/P8_VENICE.config -echo "+++ Update Chip EC levels." +echo "+++ Update Chip EC levels (SW106529)." sed -i -e's/SETENV GFW_P8_VENICE_PROC_EC.*/SETENV GFW_P8_VENICE_PROC_EC 10/' $sb/simu/configs/P8_VENICE.config sed -i -e's/SETENV GFW_P8_VENICE_CENTAUR_EC.*/SETENV GFW_P8_VENICE_CENTAUR_EC 10/' $sb/simu/configs/P8_VENICE.config sed -i -e's/SETENV GFW_P8_SALERNO_PROC_EC.*/SETENV GFW_P8_SALERNO_PROC_EC 10/' $sb/simu/configs/P8_SALERNO.config +echo "+++ Add some scom regs to centaur.chip (SW106529)." +mkdir -p $sb/simu/data/cec-chip/ +cp --update $BACKING_BUILD/src/simu/data/cec-chip/centaur.chip $sb/simu/data/cec-chip/centaur.chip.orig +grep -v DONE $sb/simu/data/cec-chip/centaur.chip.orig > $sb/simu/data/cec-chip/centaur.chip +echo "SCOMREGS # List all scom registers" >> $sb/simu/data/cec-chip/centaur.chip +echo " 0x00012345 #fake register for testing" >> $sb/simu/data/cec-chip/centaur.chip +echo " 0x0FFFFFFF #fake register for testing" >> $sb/simu/data/cec-chip/centaur.chip +echo " 0x02011672 #MBU.MBS.MCBISTS01.SCOMFIR.MCBCMA1Q" >> $sb/simu/data/cec-chip/centaur.chip +echo " 0x02011403 #MBU.MBS.MBS_FIR_MASK_REG" >> $sb/simu/data/cec-chip/centaur.chip +echo "END" >> $sb/simu/data/cec-chip/centaur.chip +echo "DONE" >> $sb/simu/data/cec-chip/centaur.chip echo "+++ Update to new simics build." mkdir -p $sb/simu/data |
