diff options
| author | Dan Crowell <dcrowell@us.ibm.com> | 2011-11-14 15:32:25 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2011-11-16 10:53:41 -0600 |
| commit | b38ef8d4d73eb72e4a2a9b98b046012f3d48ee13 (patch) | |
| tree | 20ea1b7c1148ce08d44b7306d0246d7ed2c06b0d /src/build/citest | |
| parent | 6f1adaf68285ef70e1c69d57b01c5c7b6d7fb2e6 (diff) | |
| download | talos-hostboot-b38ef8d4d73eb72e4a2a9b98b046012f3d48ee13.tar.gz talos-hostboot-b38ef8d4d73eb72e4a2a9b98b046012f3d48ee13.zip | |
Enabling FSI to remote Centaurs (SW107421 is fixed)
Change-Id: I2eaef856d94a4d84db729e1f9d1e9b5b0f8d0845
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/496
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/build/citest')
| -rwxr-xr-x | src/build/citest/etc/workarounds.presimsetup | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/build/citest/etc/workarounds.presimsetup b/src/build/citest/etc/workarounds.presimsetup index 4dd47b267..e35dbf2f3 100755 --- a/src/build/citest/etc/workarounds.presimsetup +++ b/src/build/citest/etc/workarounds.presimsetup @@ -33,6 +33,8 @@ cp --update $BACKING_BUILD/src/simu/configs/P8_SALERNO.config $sb/simu/configs sed -i -e's/SETENV GFW_P8_SALERNO_L3_MB_SIZE.*/SETENV GFW_P8_SALERNO_L3_MB_SIZE 8/' $sb/simu/configs/P8_SALERNO.config # Backing build already contains 910431. Leave this workaround here for future scomdef files #sed -i -e's/SETENV GFW_P8_SALERNO_MODEL_EC.*/SETENV GFW_P8_SALERNO_MODEL_EC 910431/' $sb/simu/configs/P8_SALERNO.config +echo "SETENV GFW_SIMICS_ENV_TEST_MODE no" >> $sb/simu/configs/P8_SALERNO.config +echo "SETENV GFW_P8_SALERNO_ENABLE_P8_PROC no" >> $sb/simu/configs/P8_SALERNO.config echo "+++ Copy desired VENICE config file to sandbox and modify L3 to 8MB." mkdir -p $sb/simu/configs @@ -40,6 +42,9 @@ cp --update $BACKING_BUILD/src/simu/configs/P8_VENICE.config $sb/simu/configs sed -i -e's/SETENV GFW_P8_VENICE_L3_MB_SIZE.*/SETENV GFW_P8_VENICE_L3_MB_SIZE 8/' $sb/simu/configs/P8_VENICE.config # Backing build already contains 910431. Leave this workaround here for future scomdef files #sed -i -e's/SETENV GFW_P8_VENICE_MODEL_EC.*/SETENV GFW_P8_VENICE_MODEL_EC 910431/' $sb/simu/configs/P8_VENICE.config +echo "SETENV GFW_SIMICS_ENV_TEST_MODE no" >> $sb/simu/configs/P8_VENICE.config +echo "SETENV GFW_P8_VENICE_ENABLE_P8_PROC no" >> $sb/simu/configs/P8_VENICE.config + echo "+++ Update Chip EC levels (SW106529)." sed -i -e's/SETENV GFW_P8_VENICE_PROC_EC.*/SETENV GFW_P8_VENICE_PROC_EC 10/' $sb/simu/configs/P8_VENICE.config @@ -52,7 +57,6 @@ cp --update $BACKING_BUILD/src/simu/data/cec-chip/centaur.chip $sb/simu/data/cec grep -v DONE $sb/simu/data/cec-chip/centaur.chip.orig > $sb/simu/data/cec-chip/centaur.chip echo "SCOMREGS # List all scom registers" >> $sb/simu/data/cec-chip/centaur.chip echo " 0x00012345 #fake register for testing" >> $sb/simu/data/cec-chip/centaur.chip -echo " 0x0FFFFFFF #fake register for testing" >> $sb/simu/data/cec-chip/centaur.chip echo " 0x02011672 #MBU.MBS.MCBISTS01.SCOMFIR.MCBCMA1Q" >> $sb/simu/data/cec-chip/centaur.chip echo " 0x02011403 #MBU.MBS.MBS_FIR_MASK_REG" >> $sb/simu/data/cec-chip/centaur.chip echo "END" >> $sb/simu/data/cec-chip/centaur.chip @@ -61,7 +65,7 @@ echo "DONE" >> $sb/simu/data/cec-chip/centaur.chip echo "+++ Update to new simics build." mkdir -p $sb/simu/data egrep -v "WSALIAS HOSTBOOT_LEVEL FIPSLEVEL|WSALIAS HOSTBOOT_LEVEL SIMICSLEVEL" $BACKING_BUILD/src/simu/data/simicsInfo > $sb/simu/data/simicsInfo -echo "WSALIAS HOSTBOOT_LEVEL FIPSLEVEL env/gfwa/simics-4.2.0/simics-4.2.82/fips/fld36/fi111019b700.42" >> $sb/simu/data/simicsInfo +echo "WSALIAS HOSTBOOT_LEVEL FIPSLEVEL env/gfwa/simics-4.2.0/simics-4.2.82/fips/fld36/fi111110b700.42" >> $sb/simu/data/simicsInfo echo "WSALIAS HOSTBOOT_LEVEL SIMICSLEVEL env/vtechb/simics-4.2.0/simics-4.2.82/bin" >> $sb/simu/data/simicsInfo echo "+++ New simics build (fi111013b700.42) needs some new files." |
