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| author | Thi Tran <thi@us.ibm.com> | 2013-01-07 15:11:58 -0600 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-01-19 14:37:56 -0600 |
| commit | 5dccb59031180c1cbd467ec36d77f63b62de04ce (patch) | |
| tree | 4888e8a340ea5603cf6bc578e5d706e0ac32e3d3 /src/build/citest | |
| parent | 63a1ec42cc6b0a3e63112535e07c24e68d798397 (diff) | |
| download | talos-hostboot-5dccb59031180c1cbd467ec36d77f63b62de04ce.tar.gz talos-hostboot-5dccb59031180c1cbd467ec36d77f63b62de04ce.zip | |
Updated VPO tools and proc_start_clock_chiplets v1.10
Change-Id: I1c70b41527a5de809d3f8f2f3f6bef64abccf1c2
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2869
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/build/citest')
| -rw-r--r-- | src/build/citest/etc/patches/patchlist.txt | 8 | ||||
| -rw-r--r-- | src/build/citest/etc/patches/s1.act.proc_start_clock_chiplets_patch | 13 | ||||
| -rwxr-xr-x | src/build/citest/etc/workarounds.postsimsetup | 8 |
3 files changed, 29 insertions, 0 deletions
diff --git a/src/build/citest/etc/patches/patchlist.txt b/src/build/citest/etc/patches/patchlist.txt index 5c8c92fb3..67c4cb454 100644 --- a/src/build/citest/etc/patches/patchlist.txt +++ b/src/build/citest/etc/patches/patchlist.txt @@ -4,3 +4,11 @@ Brief description of the problem or reason for patch -CMVC: Defect/Req for checking the changes into fips810 -Files: list of files -Coreq: list of associated changes, e.g. workarounds.presimsetup + +proc_start_clock_chiplets v1.10 requires some clock bits to be set in the clock status registers +at the time when it runs. Action file need to be updated to set these bits when at the time when +instructions are started +-RTC: Task 61816 will remove this patch +-CMVC: 865799 +-Files: s1.act_proc_start_clock_chiplets.patch +-Coreq: None
\ No newline at end of file diff --git a/src/build/citest/etc/patches/s1.act.proc_start_clock_chiplets_patch b/src/build/citest/etc/patches/s1.act.proc_start_clock_chiplets_patch new file mode 100644 index 000000000..1ddb9d540 --- /dev/null +++ b/src/build/citest/etc/patches/s1.act.proc_start_clock_chiplets_patch @@ -0,0 +1,13 @@ +--- s1.act_sandbox 2013-01-07 14:53:52.585244917 -0600 ++++ s1.act_updated 2013-01-07 14:54:39.095617417 -0600 +@@ -57,7 +57,9 @@ + EFFECT: TARGET=[FSIMBOX(0x1C)] OP=[OR,BUF] DATA=[LITERAL(64,000FFFFF 00000000)] + + #Also has effect of causing clocks on +- EFFECT: TARGET=[REG(0x08030008)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,000007FF FFFFFFFF)] ++ EFFECT: TARGET=[REG(0x08030008)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,007FFFFF FFFFFFFF)] ++ EFFECT: TARGET=[REG(0x04030008)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00003FFF FFFFFFFF)] ++ EFFECT: TARGET=[REG(0x09030008)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,000E07FF FFFFFFFF)] + EFFECT: TARGET=[LOGIC(0xFF000001)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,0xFDB40000 0x00000001)] + EFFECT: TARGET=[LOGIC(0xFF000001)] OP=[BIT,ON] BIT=[17] # EX5 vital + EFFECT: TARGET=[LOGIC(0xFF000001)] OP=[BIT,ON] BIT=[18] # EX5 diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup index 40bf41a1a..c666adb01 100755 --- a/src/build/citest/etc/workarounds.postsimsetup +++ b/src/build/citest/etc/workarounds.postsimsetup @@ -25,3 +25,11 @@ ## Workarounds that are run after start_simics is executed for the first time ## to setup the sandbox ## + +echo "+++ Updating s1.act" +mkdir -p $sb/simu/data/cec-chip +cp $BACKING_BUILD/src/simu/data/cec-chip/s1.act $sb/simu/data/cec-chip + +## Added action for proc_start_clock_chiplets v1.10 and beyond +echo "+++ Update actions for proc_start_clock_chiplets v1.10" +patch -p0 $sb/simu/data/cec-chip/s1.act $HOSTBOOTROOT/src/build/citest/etc/patches/s1.act.proc_start_clock_chiplets_patch |
