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-rw-r--r--src/build/citest/etc/patches/patchlist.txt8
-rw-r--r--src/build/citest/etc/patches/s1.act.proc_start_clock_chiplets_patch13
-rwxr-xr-xsrc/build/citest/etc/workarounds.postsimsetup8
-rwxr-xr-xsrc/build/debug/Hostboot/ContTrace.pm32
-rwxr-xr-xsrc/build/debug/vpo-debug-framework.pl38
-rw-r--r--src/build/vpo/Setup_Env46
-rw-r--r--src/build/vpo/VBU_Cacheline.pm4
-rw-r--r--src/usr/hwpf/hwp/dmi_training/dmi_training.C4
-rw-r--r--src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C263
-rw-r--r--src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.H58
10 files changed, 327 insertions, 147 deletions
diff --git a/src/build/citest/etc/patches/patchlist.txt b/src/build/citest/etc/patches/patchlist.txt
index 5c8c92fb3..67c4cb454 100644
--- a/src/build/citest/etc/patches/patchlist.txt
+++ b/src/build/citest/etc/patches/patchlist.txt
@@ -4,3 +4,11 @@ Brief description of the problem or reason for patch
-CMVC: Defect/Req for checking the changes into fips810
-Files: list of files
-Coreq: list of associated changes, e.g. workarounds.presimsetup
+
+proc_start_clock_chiplets v1.10 requires some clock bits to be set in the clock status registers
+at the time when it runs. Action file need to be updated to set these bits when at the time when
+instructions are started
+-RTC: Task 61816 will remove this patch
+-CMVC: 865799
+-Files: s1.act_proc_start_clock_chiplets.patch
+-Coreq: None \ No newline at end of file
diff --git a/src/build/citest/etc/patches/s1.act.proc_start_clock_chiplets_patch b/src/build/citest/etc/patches/s1.act.proc_start_clock_chiplets_patch
new file mode 100644
index 000000000..1ddb9d540
--- /dev/null
+++ b/src/build/citest/etc/patches/s1.act.proc_start_clock_chiplets_patch
@@ -0,0 +1,13 @@
+--- s1.act_sandbox 2013-01-07 14:53:52.585244917 -0600
++++ s1.act_updated 2013-01-07 14:54:39.095617417 -0600
+@@ -57,7 +57,9 @@
+ EFFECT: TARGET=[FSIMBOX(0x1C)] OP=[OR,BUF] DATA=[LITERAL(64,000FFFFF 00000000)]
+
+ #Also has effect of causing clocks on
+- EFFECT: TARGET=[REG(0x08030008)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,000007FF FFFFFFFF)]
++ EFFECT: TARGET=[REG(0x08030008)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,007FFFFF FFFFFFFF)]
++ EFFECT: TARGET=[REG(0x04030008)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00003FFF FFFFFFFF)]
++ EFFECT: TARGET=[REG(0x09030008)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,000E07FF FFFFFFFF)]
+ EFFECT: TARGET=[LOGIC(0xFF000001)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,0xFDB40000 0x00000001)]
+ EFFECT: TARGET=[LOGIC(0xFF000001)] OP=[BIT,ON] BIT=[17] # EX5 vital
+ EFFECT: TARGET=[LOGIC(0xFF000001)] OP=[BIT,ON] BIT=[18] # EX5
diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup
index 40bf41a1a..c666adb01 100755
--- a/src/build/citest/etc/workarounds.postsimsetup
+++ b/src/build/citest/etc/workarounds.postsimsetup
@@ -25,3 +25,11 @@
## Workarounds that are run after start_simics is executed for the first time
## to setup the sandbox
##
+
+echo "+++ Updating s1.act"
+mkdir -p $sb/simu/data/cec-chip
+cp $BACKING_BUILD/src/simu/data/cec-chip/s1.act $sb/simu/data/cec-chip
+
+## Added action for proc_start_clock_chiplets v1.10 and beyond
+echo "+++ Update actions for proc_start_clock_chiplets v1.10"
+patch -p0 $sb/simu/data/cec-chip/s1.act $HOSTBOOTROOT/src/build/citest/etc/patches/s1.act.proc_start_clock_chiplets_patch
diff --git a/src/build/debug/Hostboot/ContTrace.pm b/src/build/debug/Hostboot/ContTrace.pm
index da1b8112d..89a7472ff 100755
--- a/src/build/debug/Hostboot/ContTrace.pm
+++ b/src/build/debug/Hostboot/ContTrace.pm
@@ -1,26 +1,26 @@
#!/usr/bin/perl
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
#
-# $Source: src/build/debug/Hostboot/ContTrace.pm $
+# $Source: src/build/debug/Hostboot/ContTrace.pm $
#
-# IBM CONFIDENTIAL
+# IBM CONFIDENTIAL
#
-# COPYRIGHT International Business Machines Corp. 2012
+# COPYRIGHT International Business Machines Corp. 2012,2013
#
-# p1
+# p1
#
-# Object Code Only (OCO) source materials
-# Licensed Internal Code Source Materials
-# IBM HostBoot Licensed Internal Code
+# Object Code Only (OCO) source materials
+# Licensed Internal Code Source Materials
+# IBM HostBoot Licensed Internal Code
#
-# The source code for this program is not published or other-
-# wise divested of its trade secrets, irrespective of what has
-# been deposited with the U.S. Copyright Office.
+# The source code for this program is not published or otherwise
+# divested of its trade secrets, irrespective of what has been
+# deposited with the U.S. Copyright Office.
#
-# Origin: 30
+# Origin: 30
#
-# IBM_PROLOG_END_TAG
+# IBM_PROLOG_END_TAG
use strict;
package Hostboot::ContTrace;
@@ -91,7 +91,7 @@ sub main
return;
}
- my $trigger = ::readScom(0x00050038,8);
+ my $trigger = ::readScom(0x00050038);
if ($dbgMsg)
{
::userDisplay("$trigger...\n");
@@ -129,7 +129,7 @@ sub main
::userDisplay("$cycles\n");
}
- ::writeScom(0x00050038, 8, 0x0);
+ ::writeScom(0x00050038, 0x0);
open TRACE, ($args->{"fsp-trace"}." -s ".::getImgPath().
"hbotStringFile $fsptrace_options $fname |") || die;
diff --git a/src/build/debug/vpo-debug-framework.pl b/src/build/debug/vpo-debug-framework.pl
index 983fb19db..b13ca0a99 100755
--- a/src/build/debug/vpo-debug-framework.pl
+++ b/src/build/debug/vpo-debug-framework.pl
@@ -814,7 +814,6 @@ sub translateAddr
# Scom size is always 64-bit
#
# @param[in] scom address to read
-# @param[in] data size IN BYTES - currently ignored, assumed to be 8
#
# @return hex string containing data read
#
@@ -823,10 +822,10 @@ sub translateAddr
sub readScom
{
my $addr = shift;
- my $size = shift;
my $vpoaddr = ::translateAddr( $addr );
+ # Use simGETFAC to speed up VPO
my $cmd = "simGETFAC " .
"B0.C0.S0.P0.E8.TPC.FSI.FSI_MAILBOX.FSXCOMP." .
"FSXLOG.LBUS_MAILBOX.Q_$vpoaddr.NLC.L2 32";
@@ -839,18 +838,20 @@ sub readScom
$result =~ s/\n//g;
## debug
- ## ::userDisplay "--- readScom: ",
- ## (sprintf("0x%x-->%s, 0x%x : %s", $addr,$vpoaddr,$size,$result)), "\n";
+ #::userDisplay "--- readScom: ",
+ # (sprintf("0x%x-->%s, %s", $addr,$vpoaddr,$result)), "\n";
## comes in as a 32-bit #, need to shift 32 to match simics
- return (hex ( "0x" . $result . "00000000" ));
+ my $scomvalue = "0x" . $result;
+ $scomvalue = hex($scomvalue);
+ $scomvalue <<= 32;
+ return ($scomvalue);
}
# @sub writeScom
# @brief Write a scom address in VPO.
#
# @param[in] - scom address
-# @param[in] - data size IN BYTES - ignored, assumed to be 8
# @param[in] - binary data value. Scom value is aways assumed to be 64bits
#
# @return none
@@ -860,28 +861,13 @@ sub readScom
sub writeScom
{
my $addr = shift;
- my $size = shift;
my $value = shift;
- my $cmd = "";
-
- my $vpoaddr = ::translateAddr( $addr );
-
- ## vpo takes a 32 bit value in the lower 32 bits
- my $value32 = ( ( $value >> 32 ) & 0x00000000ffffffff );
- my $valuestr = sprintf( "0x%x", $value32 );
-
- ## debug
- ## ::userDisplay "--- writeScom: ",
- ## (sprintf("0x%x-->%s, 0x%x, %s",$addr,$vpoaddr,$size,$valuestr)), "\n";
-
- ## now go ahead and write the real value
- $cmd = "simSTKFAC " .
- "B0.C0.S0.P0.E8.TPC.FSI.FSI_MAILBOX.FSXCOMP." .
- "FSXLOG.LBUS_MAILBOX.Q_$vpoaddr.NLC.L2 $valuestr 32 -quiet";
+ my $addrstr = sprintf( "%08x", $addr );
+ my $valuestr = sprintf( "%016x", $value );
- ( system( $cmd ) == 0 )
- or die "$cmd failed, $? : $! \n";
+ # Use putscom because simPUTFAC doesn't work consistenly
+ system("putscom pu $addrstr $valuestr -cft -quiet");
return;
}
@@ -898,7 +884,7 @@ sub checkContTrace()
my $SCRATCH_MBOX0 = 0x00050038;
my $contTrace = "";
- $contTrace = ::readScom( $SCRATCH_MBOX0, 8 );
+ $contTrace = ::readScom( $SCRATCH_MBOX0 );
if ( $contTrace != 0 )
{
## activate continuous trace
diff --git a/src/build/vpo/Setup_Env b/src/build/vpo/Setup_Env
index fd452e714..e550d4bf1 100644
--- a/src/build/vpo/Setup_Env
+++ b/src/build/vpo/Setup_Env
@@ -1,26 +1,26 @@
#!/bin/sh "Use source to invoke this script"
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
#
-# $Source: src/build/vpo/Setup_Env $
+# $Source: src/build/vpo/Setup_Env $
#
-# IBM CONFIDENTIAL
+# IBM CONFIDENTIAL
#
-# COPYRIGHT International Business Machines Corp. 2012
+# COPYRIGHT International Business Machines Corp. 2012,2013
#
-# p1
+# p1
#
-# Object Code Only (OCO) source materials
-# Licensed Internal Code Source Materials
-# IBM HostBoot Licensed Internal Code
+# Object Code Only (OCO) source materials
+# Licensed Internal Code Source Materials
+# IBM HostBoot Licensed Internal Code
#
-# The source code for this program is not published or other-
-# wise divested of its trade secrets, irrespective of what has
-# been deposited with the U.S. Copyright Office.
+# The source code for this program is not published or otherwise
+# divested of its trade secrets, irrespective of what has been
+# deposited with the U.S. Copyright Office.
#
-# Origin: 30
+# Origin: 30
#
-# IBM_PROLOG_END_TAG
+# IBM_PROLOG_END_TAG
################################################################################
#
@@ -47,6 +47,7 @@
#
# Version 1.5 10-09-2012 Added m_9_g/m_10_g/m_10_h models
#
+# Version 1.6 01-03-2012 Updated for m_10_b, m_11_a
################################################################################
# Define useful pointers to automated tests/scripts
@@ -89,18 +90,17 @@ unset HB_VBUPNOR_ADDR HB_SYSMVPD_ADDR HB_SYSSPD_ADDR
Setup_MyEnv() {
# Default Sprint release
-
- sprint=hb0606a_1219.810
+ sprint=hb0107a_1250.810
# Initialize HostBoot environment/cronus/tools - note new naming convention
export AUTOVBU_CRONUS_SIM=dev
- export ISTEP_ARCHIVE=archives/12.11.15
+ export ISTEP_ARCHIVE=archives/13.01.08
export GLOBAL_DEBUG=8.VW.Vc.dG.F3.0I.E8.V
- export HB_TOOLS=$AUTOVBU_HBTOOLS_BASEDIR/rel.20121126
+ export HB_TOOLS=$AUTOVBU_HBTOOLS_BASEDIR/rel.20130110
# Select default model -- choose either VBU or VPO versions
- export VPO_MODEL=m_10_h; unset VBU_MODEL; VBUVPO=VPO
+ export VPO_MODEL=m_11_a; unset VBU_MODEL; VBUVPO=VPO
# Default AWAN request time - shorter periods get AWAN faster
@@ -270,7 +270,13 @@ Setup_MyDynamic() {
# Set other defaults based upon MODEL
case "$VPO_MODEL$VBU_MODEL"
in
- s1_e8052_nA_p8_c0400_cen1_cen081_unopt_1|s1_e8052_c0400_cen1_cen081_unopt_1|s1_e8050_c0400_cen1_cen081_unopt_1|s1_e8050_nA_p8_c0400_cen1_cen081_unopt_1|m_9_a|m_9_g|m_10_g)
+ s1_e8042_c0400_cen1_cen0*|m_10_b|s1_e8053_n8_p8_c0400_cen1_cen081_unopt_1|m_11_a)
+ export AUTOVBU_ECMD_VER=${AUTOVBU_ECMD_VER-p8s1}
+ export AWAN_CONFIG=${AWAN_CONFIG-star8b}
+ unset DEFAULT_LEVEL
+ ;;
+
+ s1_e8052_nA_p8_c0400_cen1_cen081_unopt_1|s1_e8052_c0400_cen1_cen081_unopt_1|s1_e8050_c0400_cen1_cen081_unopt_1|s1_e8050_nA_p8_c0400_cen1_cen081_unopt_1|m_9_a|m_9_g|m_10_g)
export AUTOVBU_ECMD_VER=${AUTOVBU_ECMD_VER-p8s1}
export AWAN_CONFIG=${AWAN_CONFIG-star12b}
unset DEFAULT_LEVEL
diff --git a/src/build/vpo/VBU_Cacheline.pm b/src/build/vpo/VBU_Cacheline.pm
index 8ab892149..254b24598 100644
--- a/src/build/vpo/VBU_Cacheline.pm
+++ b/src/build/vpo/VBU_Cacheline.pm
@@ -6,7 +6,7 @@
#
# IBM CONFIDENTIAL
#
-# COPYRIGHT International Business Machines Corp. 2011,2012
+# COPYRIGHT International Business Machines Corp. 2011,2013
#
# p1
#
@@ -79,7 +79,7 @@ my $CORE = "-cft";
my $SIM_CLOCKS = $ENV{'HB_SIMCLOCKS'};
if ( ! defined ( $SIM_CLOCKS ) || $SIM_CLOCKS == 0 ) {
- $SIM_CLOCKS = "5000000";
+ $SIM_CLOCKS = "4000000";
}
print "clocks=$SIM_CLOCKS\n";
diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_training.C b/src/usr/hwpf/hwp/dmi_training/dmi_training.C
index 2515e393d..d1a8f9189 100644
--- a/src/usr/hwpf/hwp/dmi_training/dmi_training.C
+++ b/src/usr/hwpf/hwp/dmi_training/dmi_training.C
@@ -591,10 +591,6 @@ void* call_dmi_io_dccal( void *io_pArgs )
return l_StepError.getErrorHandle();
}
- // TODO: RTC 60627
- // Reinstate this to enable dmi_io_dccal
- return l_StepError.getErrorHandle();
-
TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"call_dmi_io_dccal entry" );
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C b/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C
index ae76464fe..c173a7bf8 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C
@@ -1,27 +1,26 @@
-/* IBM_PROLOG_BEGIN_TAG
- * This is an automatically generated prolog.
- *
- * $Source: src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C $
- *
- * IBM CONFIDENTIAL
- *
- * COPYRIGHT International Business Machines Corp. 2012
- *
- * p1
- *
- * Object Code Only (OCO) source materials
- * Licensed Internal Code Source Materials
- * IBM HostBoot Licensed Internal Code
- *
- * The source code for this program is not published or other-
- * wise divested of its trade secrets, irrespective of what has
- * been deposited with the U.S. Copyright Office.
- *
- * Origin: 30
- *
- * IBM_PROLOG_END_TAG
- */
-// $Id: proc_start_clocks_chiplets.C,v 1.5 2012/08/08 12:05:11 rkoester Exp $
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C $ */
+/* */
+/* IBM CONFIDENTIAL */
+/* */
+/* COPYRIGHT International Business Machines Corp. 2012,2013 */
+/* */
+/* p1 */
+/* */
+/* Object Code Only (OCO) source materials */
+/* Licensed Internal Code Source Materials */
+/* IBM HostBoot Licensed Internal Code */
+/* */
+/* The source code for this program is not published or otherwise */
+/* divested of its trade secrets, irrespective of what has been */
+/* deposited with the U.S. Copyright Office. */
+/* */
+/* Origin: 30 */
+/* */
+/* IBM_PROLOG_END_TAG */
+// $Id: proc_start_clocks_chiplets.C,v 1.10 2012/12/12 10:43:10 rkoester Exp $
// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_start_clocks_chiplets.C,v $
//------------------------------------------------------------------------------
// *|
@@ -229,27 +228,128 @@ fapi::ReturnCode proc_start_clocks_chiplet_clear_clk_scansel_reg(
//------------------------------------------------------------------------------
+// function: utility subroutine to get partial good vector from SEEPROM
+// parameters: i_target => chip target
+// i_chiplet_base_addr => base SCOM address for chiplet
+// i_chiplet_reg_vec => output vector
+// returns: FAPI_RC_SUCCESS if operation was successful, else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_start_clocks_get_partial_good_vector(
+ const fapi::Target& i_target,
+ const uint32_t i_chiplet_base_addr,
+ uint64_t * o_chiplet_reg_vec
+ )
+{
+ fapi::ReturnCode rc;
+// uint32_t rc_ecmd = 0;
+
+// uint8_t chiplet = 0;
+ uint64_t partial_good_regions[32];
+
+ FAPI_DBG("proc_start_clocks_get_partial_good_vector: Start");
+
+ do
+ {
+
+ FAPI_DBG("proc_start_clocks_get_partial_good_vector: Get attribute ATTR_CHIP_REGIONS_TO_ENABLE (partial good region data) " );
+ rc = FAPI_ATTR_GET( ATTR_CHIP_REGIONS_TO_ENABLE, &i_target, partial_good_regions);
+ if (rc) {
+ FAPI_ERR("fapi_attr_get( ATTR_CHIP_REGIONS_TO_ENABLE ) failed. With rc = 0x%x",
+ (uint32_t) rc );
+ break;
+ }
+
+
+// expectecd value out of SEEPROM (all good)
+// Partial Good Region Pattern are:
+// XBUS = 0xF000
+// ABUS = 0xE100
+// PCIE = 0xF700
+
+
+ FAPI_DBG("proc_start_clocks_get_partial_good_vector: start assignment of the partial good vector per chiplet");
+
+ switch (i_chiplet_base_addr)
+ {
+
+ case X_BUS_CHIPLET_0x04000000:
+ FAPI_DBG("proc_start_clocks_get_partial_good_vector: XBUS, attribute for XBUS (%016llX)", partial_good_regions[4]);
+ *o_chiplet_reg_vec = partial_good_regions[4];
+ break;
+
+
+ case A_BUS_CHIPLET_0x08000000:
+ FAPI_DBG("proc_start_clocks_get_partial_good_vector: ABUS, attribute for ABUS (%016llX)", partial_good_regions[8]);
+ *o_chiplet_reg_vec = partial_good_regions[8];
+ break;
+
+ case PCIE_CHIPLET_0x09000000:
+ FAPI_DBG("proc_start_clocks_get_partial_good_vector: PCIE, attribute for PCIE (%016llX)", partial_good_regions[9]);
+ *o_chiplet_reg_vec = partial_good_regions[9];
+ break;
+
+ default:
+
+ FAPI_ERR("proc_start_clocks_get_partial_good_vector: invalid chiplet base address selected when selecting par. good vector (0x%08X)",
+ i_chiplet_base_addr);
+ uint32_t CHIPLET_BASE_SCOM_ADDR = i_chiplet_base_addr;
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_CHIPLETS_PARTIAL_GOOD_ERR);
+ break;
+
+ }
+
+ FAPI_DBG("proc_start_clocks_get_partial_good_vector: picked partial good regions vector is (%016llX)", *o_chiplet_reg_vec);
+
+
+ } while(0);
+
+ FAPI_DBG("proc_start_clocks_get_partial_good_vector: End");
+
+ return rc;
+}
+
+
+//------------------------------------------------------------------------------
// function: utility subroutine to set clock region register (starts clocks)
// parameters: i_target => chip target
// i_chiplet_base_addr => base SCOM address for chiplet
+// i_chiplet_reg_vec => vector from SEEPROM with partial good
+// clock regions
// returns: FAPI_RC_SUCCESS if operation was successful, else error
+
//------------------------------------------------------------------------------
fapi::ReturnCode proc_start_clocks_chiplet_set_clk_region_reg(
const fapi::Target& i_target,
- const uint32_t i_chiplet_base_addr)
+ const uint32_t i_chiplet_base_addr,
+ const uint64_t i_chiplet_reg_vec,
+ uint64_t * o_chiplet_clkreg_vec
+ )
+
+
{
fapi::ReturnCode rc;
uint32_t rc_ecmd = 0;
ecmdDataBufferBase data(64);
uint32_t scom_addr = i_chiplet_base_addr |
GENERIC_CLK_REGION_0x00030006;
+ uint64_t extracted_rec_vec;
+ uint64_t clk_region_start_nsl_ary_masked;
+ uint64_t clk_region_start_all_masked;
FAPI_DBG("proc_start_clocks_chiplet_set_clk_region_reg: Start");
do
{
+
+
+ // bitwise ORing of input vector
+ extracted_rec_vec = PROC_START_CLOCKS_CHIPLETS_CLOCK_REGION_MANIPULATION | i_chiplet_reg_vec;
+
// start NSL/array clocks
- rc_ecmd |= data.setDoubleWord(0, PROC_START_CLOCKS_CHIPLETS_CLK_REGION_REG_START_NSL_ARY);
+
+ clk_region_start_nsl_ary_masked = PROC_START_CLOCKS_CHIPLETS_CLK_REGION_REG_START_NSL_ARY & extracted_rec_vec;
+
+ rc_ecmd |= data.setDoubleWord(0, clk_region_start_nsl_ary_masked);
if (rc_ecmd)
{
FAPI_ERR("proc_start_clocks_chiplet_set_clk_region_reg: Error 0x%x setting up data buffer for NSL/ARY clock start",
@@ -267,7 +367,14 @@ fapi::ReturnCode proc_start_clocks_chiplet_set_clk_region_reg(
}
// start all clocks
- rc_ecmd |= data.setDoubleWord(0, PROC_START_CLOCKS_CHIPLETS_CLK_REGION_REG_START_ALL);
+
+ clk_region_start_all_masked = PROC_START_CLOCKS_CHIPLETS_CLK_REGION_REG_START_ALL & extracted_rec_vec;
+
+ // output: value written into clk_region register, reused for status register checking
+
+ *o_chiplet_clkreg_vec = clk_region_start_all_masked;
+
+ rc_ecmd |= data.setDoubleWord(0, clk_region_start_all_masked);
if (rc_ecmd)
{
FAPI_ERR("proc_start_clocks_chiplet_set_clk_region_reg: Error 0x%x setting up data buffer for SL/NSL/ARY clock start",
@@ -297,8 +404,8 @@ fapi::ReturnCode proc_start_clocks_chiplet_set_clk_region_reg(
// all desired clock domains have been started
// parameters: i_target => chip target
// i_chiplet_base_addr => base SCOM address for chiplet
-// i_status_reg_exp => expected value for clock status register
-// after clock start
+// i_chiplet_reg_vec => region vector of SEEPROM for clock regions
+// need to be turned on
// returns: FAPI_RC_SUCCESS if operation was successful, else
// RC_PROC_START_CLOCKS_CHIPLETS_CLK_STATUS_ERR if status register
// data does not match expected pattern
@@ -306,17 +413,22 @@ fapi::ReturnCode proc_start_clocks_chiplet_set_clk_region_reg(
fapi::ReturnCode proc_start_clocks_chiplet_check_clk_status_reg(
const fapi::Target& i_target,
const uint32_t i_chiplet_base_addr,
- const uint64_t i_status_reg_exp)
+ const uint64_t i_chiplet_clkreg_vec)
{
fapi::ReturnCode rc;
+ uint32_t rc_ecmd = 0;
+ ecmdDataBufferBase vec_data(64);
ecmdDataBufferBase status_data(64);
+ ecmdDataBufferBase exp_data(64);
uint32_t scom_addr = i_chiplet_base_addr |
GENERIC_CLK_STATUS_0x00030008;
+ const uint32_t xbus = X_BUS_CHIPLET_0x04000000;
FAPI_DBG("proc_start_clocks_chiplet_check_clk_status_reg: Start");
do
{
+
// read clock status register
rc = fapiGetScom(i_target, scom_addr, status_data);
if (rc)
@@ -326,12 +438,52 @@ fapi::ReturnCode proc_start_clocks_chiplet_check_clk_status_reg(
break;
}
+ // intialize reference databuffer
+ rc_ecmd |= vec_data.flushTo0();
+ // load it with reference data
+ rc_ecmd |= vec_data.setDoubleWord(0, i_chiplet_clkreg_vec);
+ // generate expected value databuffer
+ rc_ecmd |= exp_data.flushTo1();
+
+ if ( i_chiplet_base_addr == xbus)
+ {
+
+ if ( vec_data.isBitSet(4)) { rc_ecmd |= exp_data.clearBit(0,3); }
+ if ( vec_data.isBitSet(5)) { rc_ecmd |= exp_data.clearBit(3,6); }
+ if ( vec_data.isBitSet(6)) { rc_ecmd |= exp_data.clearBit(9,6); }
+ if ( vec_data.isBitSet(7)) { rc_ecmd |= exp_data.clearBit(15,3);}
+
+ }
+
+ else
+ {
+
+ if ( vec_data.isBitSet(4)) { rc_ecmd |= exp_data.clearBit(0,3); }
+ if ( vec_data.isBitSet(5)) { rc_ecmd |= exp_data.clearBit(3,3); }
+ if ( vec_data.isBitSet(6)) { rc_ecmd |= exp_data.clearBit(6,3); }
+ if ( vec_data.isBitSet(7)) { rc_ecmd |= exp_data.clearBit(9,3); }
+ if ( vec_data.isBitSet(9)) { rc_ecmd |= exp_data.clearBit(15,3);}
+ if ( vec_data.isBitSet(10)) { rc_ecmd |= exp_data.clearBit(18,3);}
+ if ( vec_data.isBitSet(11)) { rc_ecmd |= exp_data.clearBit(21,3);}
+
+ }
+
+
+ if (rc_ecmd)
+ {
+ FAPI_ERR("proc_start_clocks_chiplet_check_clk_status_reg: Error 0x%x setting up data buffer to set clock status",
+ rc_ecmd);
+ rc.setEcmdError(rc_ecmd);
+ break;
+ }
+
+
// check that value matches expected pattern
// set a unique HWP_ERROR
- if (status_data.getDoubleWord(0) != i_status_reg_exp)
+ if (status_data.getDoubleWord(0) != exp_data.getDoubleWord(0))
{
FAPI_ERR("proc_start_clocks_chiplet_check_clk_status_reg: Clock status register actual value (%016llX) does not match expected value (%016llX)",
- status_data.getDoubleWord(0), i_status_reg_exp);
+ status_data.getDoubleWord(0), exp_data.getDoubleWord(0));
ecmdDataBufferBase & STATUS_REG = status_data;
uint32_t CHIPLET_BASE_SCOM_ADDR = i_chiplet_base_addr;
FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_CHIPLETS_CLK_STATUS_ERR);
@@ -504,15 +656,19 @@ fapi::ReturnCode proc_start_clocks_chiplet_check_fir(
//------------------------------------------------------------------------------
fapi::ReturnCode proc_start_clocks_generic_chiplet(
const fapi::Target& i_target,
- const uint32_t i_chiplet_base_addr,
- const uint64_t i_status_reg_exp)
+ const uint32_t i_chiplet_base_addr)
+
{
fapi::ReturnCode rc;
+ uint64_t chiplet_reg_vec;
+ uint64_t chiplet_clkreg_vec;
FAPI_DBG("proc_start_clocks_generic_chiplet: Start");
do
{
+
+
// clear chiplet fence in GP3 register
FAPI_DBG("Writing GP3 AND mask to clear chiplet fence ...");
rc = proc_start_clocks_chiplet_clear_chiplet_fence(i_target,
@@ -553,10 +709,28 @@ fapi::ReturnCode proc_start_clocks_generic_chiplet(
break;
}
+ // pick partial good region vector from SEEPROM
+ FAPI_DBG("Get partial good region vector ...");
+ rc = proc_start_clocks_get_partial_good_vector(i_target,
+ i_chiplet_base_addr,
+ & chiplet_reg_vec
+ );
+ if (rc)
+ {
+ FAPI_ERR("proc_start_clocks_partial_good_vector: Error getting partial good region vector");
+ break;
+ }
+
+
// write clock region register to start clocks
FAPI_DBG("Writing clock region register to start clocks ...");
rc = proc_start_clocks_chiplet_set_clk_region_reg(i_target,
- i_chiplet_base_addr);
+ i_chiplet_base_addr,
+ chiplet_reg_vec,
+ & chiplet_clkreg_vec
+ );
+
+
if (rc)
{
FAPI_ERR("proc_start_clocks_generic_chiplet: Error writing clock region register");
@@ -564,10 +738,10 @@ fapi::ReturnCode proc_start_clocks_generic_chiplet(
}
// check clock status register to ensure that all clocks are started
- FAPI_DBG("Chcecking clock status register ...");
+ FAPI_DBG("Checking clock status register ...");
rc = proc_start_clocks_chiplet_check_clk_status_reg(i_target,
i_chiplet_base_addr,
- i_status_reg_exp);
+ chiplet_clkreg_vec);
if (rc)
{
FAPI_ERR("proc_start_clocks_generic_chiplet: Error checking clock status register");
@@ -630,8 +804,7 @@ fapi::ReturnCode proc_start_clocks_chiplets(const fapi::Target& i_target,
FAPI_DBG("Starting X bus chiplet clocks ...");
rc = proc_start_clocks_generic_chiplet(
i_target,
- X_BUS_CHIPLET_0x04000000,
- PROC_START_CLOCKS_CHIPLETS_XBUS_CLK_STATUS_REG_EXP);
+ X_BUS_CHIPLET_0x04000000);
if (rc)
{
break;
@@ -643,11 +816,7 @@ fapi::ReturnCode proc_start_clocks_chiplets(const fapi::Target& i_target,
FAPI_DBG("Starting A bus chiplet clocks ...");
rc = proc_start_clocks_generic_chiplet(
i_target,
- // TODO MJJ Updated to A_BUS_CHIPLET_0x08000000 to match new
- // p8_scom_addresses, this will go away when this HWP is
- // refreshed
- A_BUS_CHIPLET_0x08000000,
- PROC_START_CLOCKS_CHIPLETS_ABUS_CLK_STATUS_REG_EXP);
+ A_BUS_CHIPLET_0x08000000);
if (rc)
{
break;
@@ -659,11 +828,7 @@ fapi::ReturnCode proc_start_clocks_chiplets(const fapi::Target& i_target,
FAPI_DBG("Starting PCIE chiplet clocks ...");
rc = proc_start_clocks_generic_chiplet(
i_target,
- // TODO MJJ Updated to PCIE_CHIPLET_0x09000000 to match new
- // p8_scom_addresses, this will go away when this HWP is
- // refreshed
- PCIE_CHIPLET_0x09000000,
- PROC_START_CLOCKS_CHIPLETS_PCIE_CLK_STATUS_REG_EXP);
+ PCIE_CHIPLET_0x09000000);
if (rc)
{
break;
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.H b/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.H
index bedc140a2..c45ff234f 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.H
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.H
@@ -1,27 +1,26 @@
-/* IBM_PROLOG_BEGIN_TAG
- * This is an automatically generated prolog.
- *
- * $Source: src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.H $
- *
- * IBM CONFIDENTIAL
- *
- * COPYRIGHT International Business Machines Corp. 2012
- *
- * p1
- *
- * Object Code Only (OCO) source materials
- * Licensed Internal Code Source Materials
- * IBM HostBoot Licensed Internal Code
- *
- * The source code for this program is not published or other-
- * wise divested of its trade secrets, irrespective of what has
- * been deposited with the U.S. Copyright Office.
- *
- * Origin: 30
- *
- * IBM_PROLOG_END_TAG
- */
-// $Id: proc_start_clocks_chiplets.H,v 1.3 2012/02/19 15:40:41 jmcgill Exp $
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.H $ */
+/* */
+/* IBM CONFIDENTIAL */
+/* */
+/* COPYRIGHT International Business Machines Corp. 2012,2013 */
+/* */
+/* p1 */
+/* */
+/* Object Code Only (OCO) source materials */
+/* Licensed Internal Code Source Materials */
+/* IBM HostBoot Licensed Internal Code */
+/* */
+/* The source code for this program is not published or otherwise */
+/* divested of its trade secrets, irrespective of what has been */
+/* deposited with the U.S. Copyright Office. */
+/* */
+/* Origin: 30 */
+/* */
+/* IBM_PROLOG_END_TAG */
+// $Id: proc_start_clocks_chiplets.H,v 1.5 2012/12/07 18:15:17 jmcgill Exp $
// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_start_clocks_chiplets.H,v $
//------------------------------------------------------------------------------
// *|
@@ -84,15 +83,14 @@ const uint8_t GP0_PERV_FENCE_BIT = 63;
const uint64_t PROC_START_CLOCKS_CHIPLETS_CLK_REGION_REG_START_NSL_ARY = 0x4FE0060000000000ull;
const uint64_t PROC_START_CLOCKS_CHIPLETS_CLK_REGION_REG_START_ALL = 0x4FE00E0000000000ull;
-// Clock Status Register expected pattern
-// TODO: reconcile expected value wiht pervasive spreadsheet
-const uint64_t PROC_START_CLOCKS_CHIPLETS_XBUS_CLK_STATUS_REG_EXP = 0x0000001FFFFFFFFFull;
-const uint64_t PROC_START_CLOCKS_CHIPLETS_ABUS_CLK_STATUS_REG_EXP = 0x000007FFFFFFFFFFull;
-const uint64_t PROC_START_CLOCKS_CHIPLETS_PCIE_CLK_STATUS_REG_EXP = 0x000007FFFFFFFFFFull;
-
// Chiplet FIR register expected pattern
const uint64_t PROC_START_CLOCKS_CHIPLETS_CHIPLET_FIR_REG_EXP = 0x0000000000000000ull;
+
+// Input clock region vector mask (for bit manipulation of clock regions)
+const uint64_t PROC_START_CLOCKS_CHIPLETS_CLOCK_REGION_MANIPULATION = 0xF0000FFFFFFFFFFFull;
+
+
//------------------------------------------------------------------------------
// Function prototype
//------------------------------------------------------------------------------
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