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* * config/sparc/sparc-protos.h (sparc_absnegfloat_split_legitimate):ebotcazou2014-05-141-130/+161
* PR target/60941ebotcazou2014-04-251-13/+0
* * config/sparc/sparc.c (sparc_do_work_around_errata): Implement workebotcazou2014-03-201-2/+6
* * config/sparc/sparc-protos.h (tls_call_delay): Delete.ebotcazou2014-03-151-47/+27
* Update copyright years in gcc/rsandifo2014-01-021-1/+1
* PR target/59316ebotcazou2013-12-061-16/+26
* PR bootstrap/58509ebotcazou2013-10-141-39/+48
* * config.gcc (sparc*-*-*): Accept leon3 processor.ebotcazou2013-07-221-1/+2
* * config/sparc/sparc.c (sparc_expand_vec_perm_bmask): Use %g0 asebotcazou2013-05-281-1/+1
* * doc/invoke.texi (SPARC Options): Document -mfix-ut699.ebotcazou2013-05-281-5/+37
* Improve cstore code generation on 64-bit sparc.davem2013-04-101-93/+44
* * config/sparc/sparc.md: Use define_c_enum for "unspec" and "unspecv".steven2013-04-091-82/+82
* * config/sparc/sparc.c (sparc_emit_probe_stack_range): Fix smallebotcazou2013-03-231-2/+2
* Update copyright years in gcc/rsandifo2013-01-101-3/+1
* PR target/54121ebotcazou2012-12-111-7/+7
* Add support for sparc fused compare-and-branch.davem2012-11-151-7/+74
* Revert sparc "U" constraint removal.davem2012-11-071-8/+8
* Remove unnecessary sparc constraint.davem2012-10-251-8/+8
* Make Niagara-4 instruction scheduling more accurate.davem2012-10-101-23/+23
* * config/sparc/predicates.md (input_operand): Do not consider TImodeebotcazou2012-09-131-1/+159
* * config/sparc/sparc.md (adddi3_insn_sp32): Add earlyclobber.ebotcazou2012-07-191-1/+1
* * output.h: (current_function_is_leaf,steven2012-06-241-1/+1
* gcc/rsandifo2012-05-051-1/+1
* Add sparc Niagara4 scheduling description and tweaks.davem2012-04-261-0/+1
* Fix sparc instruction type settings and sched bugs.davem2012-04-261-27/+42
* Explain why we don't use RDPC for sparc PIC register setup.davem2012-02-211-0/+4
* * config/sparc/sparc.c (sparc_flat_expand_prologue): Use emit_use.ebotcazou2012-02-111-29/+4
* * config/sparc/sparc.md (UNSPEC_FRAME_BLOCKAGE): New constant.ebotcazou2011-12-161-0/+20
* sparc: Convert to atomic_load/store.rth2011-11-301-0/+1
* Revert sparc vec_init improvements as they cause 64-bit regressions.davem2011-11-111-54/+0
* * config/sparc/sparc.c (output_v8plus_shift): Take INSN parameter firstebotcazou2011-11-091-3/+3
* Get rid of sparc's UNSPEC_SHORT_LOAD.davem2011-11-071-11/+22
* More improvements to sparc VIS vec_init code generation.davem2011-11-061-0/+43
* * config/sparc/sparc.md (movtf_insn_sp32_no_fpu): Consolidate into...ebotcazou2011-11-031-36/+11
* PR target/50945ebotcazou2011-11-021-18/+17
* Add vcond/vcondu patterns to sparc backend.davem2011-11-011-0/+30
* Allow zero operand in sparc VIS3 cmask patterns.davem2011-10-311-3/+3
* Add support for the VIS3 addxc instruction.davem2011-10-281-5/+75
* Fix constraint on 64-bit VIS3 vector moves.davem2011-10-281-2/+2
* Improve sparc setcc generation and add testcases.davem2011-10-261-0/+59
* Canonicalize sparc movcc patterns such that operand 0 always appears in opera...davem2011-10-261-130/+67
* Segregate sparc FP/VEC constant constraints.davem2011-10-241-12/+12
* Consolidate some sparc insn patterns using "enabled".davem2011-10-241-430/+58
* Add support for sparc VIS3 fp<-->int moves.davem2011-10-241-32/+343
* Factor out common tests in 8-byte reg/reg move splitters on 32-bit sparc.davem2011-10-231-10/+4
* Add missing fzero/fone cases to DImode move on 32-bit v9 sparc.davem2011-10-231-7/+15
* Use a macro instead of a constant to test for sparc integer regnos.davem2011-10-231-20/+20
* * config/sparc/sparc.md (in_call_delay): Fix formatting issues.ebotcazou2011-10-181-6/+6
* Add sparc vec_perm patterns when VIS2.davem2011-10-181-0/+37
* Fix predicates used in sparc VIS edge instructions.davem2011-10-171-34/+34
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