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ppe42-gcc
gcc-4_9_2-ppe42
GCC for the PPE42
Raptor Computing Systems
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Commit message (
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Author
Age
Files
Lines
*
unsupported insn for bswap emitted
Doug Gilbert
2017-10-06
1
-1
/
+1
*
Indicate that PPE42 fused branch instructions modify the CR
Doug Gilbert
2017-08-18
2
-16
/
+27
*
Prevent unsupported load/store index updateinstructions on PPE
Doug Gilbert
2017-02-10
1
-5
/
+119
*
Fix compile issue when compiling with gcc 6
Douglas Gilbert
2017-01-17
1
-2
/
+2
*
Fix insn attribute length field for load zero-extend operation
Doug Gilbert
2016-10-28
2
-29
/
+22
*
PPE42 compare immediate branch with immediate value out of range
Doug Gilbert
2016-09-13
1
-4
/
+21
*
requre 8 byte alignment on offsettable memory access for 64bit load/store
Doug Gilbert
2016-08-15
3
-6
/
+27
*
Add RTL to correctly handle unavailable lwzux instruction
Doug Gilbert
2016-08-15
1
-2
/
+15
*
PPE42 compiler generates invalid crnot instruction
Doug Gilbert
2016-08-15
1
-2
/
+6
*
Turn off 64bit load/stores in epilog/proglog
Doug Gilbert
2016-08-15
2
-4
/
+6
*
Fix PPE42 illegal stwux asm command
Doug Gilbert
2016-08-15
2
-2
/
+26
*
Unsigned compare immediate branch emitting wrong instructions
Doug Gilbert
2016-08-15
2
-1
/
+7
*
Remove more places lbzux was being used
Doug Gilbert
2016-08-15
1
-466
/
+507
*
Fix where signed compare should be unsigned compare
Doug Gilbert
2016-08-15
1
-11
/
+10
*
Delivered 05/2015
Doug Gilbert
2016-08-15
2
-1
/
+3
*
provide clrbwibc
Doug Gilbert
2016-08-15
2
-30
/
+45
*
bnbwi support
Doug Gilbert
2016-08-15
4
-6
/
+144
*
Add ppe405 and ppe42 cpu types
Doug Gilbert
2016-08-15
7
-111
/
+144
*
64 bit load/store peepholes
Doug Gilbert
2016-08-15
3
-13
/
+188
*
64 bit load/store
Doug Gilbert
2016-08-15
3
-19
/
+43
*
Compare-branch fused instructions
Doug Gilbert
2016-08-15
4
-31
/
+204
*
hack1
Doug Gilbert
2016-08-15
4
-890
/
+900
*
[AArch64] Restore recog state after finding pre-madd instruction
ktkachov
2014-10-29
1
-0
/
+4
*
[gcc]
wschmidt
2014-10-13
3
-5
/
+60
*
[AArch64] Add --enable-fix-cortex-a53-835769 configure-time option
ktkachov
2014-10-10
2
-1
/
+10
*
[AArch64] Implement workaround for ARM Cortex-A53 erratum 835769
ktkachov
2014-10-10
4
-0
/
+137
*
gcc/
olegendo
2014-10-08
1
-2
/
+12
*
PR target/63428
jakub
2014-10-01
1
-2
/
+2
*
[PATCH][ARM] Disable store_minmaxsi pattern for arm_restrict_i
ktkachov
2014-10-01
1
-1
/
+1
*
Backport from mainline
uros
2014-10-01
1
-6
/
+12
*
PR target/61407
fxcoudert
2014-09-29
2
-25
/
+35
*
2014-09-29 Charles Baylis <charles.baylis@linaro.org>
cbaylis
2014-09-29
4
-23
/
+31
*
* config/pa/pa.c (pa_output_function_epilogue): Only update
danglin
2014-09-28
1
-3
/
+6
*
gcc/
olegendo
2014-09-25
1
-2
/
+2
*
[gcc]
wschmidt
2014-09-25
1
-1
/
+2
*
2014-09-23 Michael Meissner <meissner@linux.vnet.ibm.com>
meissner
2014-09-23
1
-10
/
+27
*
2014-09-19 Michael Meissner <meissner@linux.vnet.ibm.com>
meissner
2014-09-19
4
-109
/
+119
*
2014-09-19 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
krebbel
2014-09-19
1
-5
/
+14
*
PR target/61853
danglin
2014-09-16
1
-2
/
+8
*
* config/msp430/msp430.md (extendhipsi2): Use 20-bit form of RLAM/RRAM.
dj
2014-09-12
1
-3
/
+3
*
Also turn off OPTION_MASK_ABI_X32 for -m16
hjl
2014-09-11
1
-2
/
+3
*
[AArch64] Cheap fix for argument types of vmull_high_lane_{us}{16,32}
jgreenhalgh
2014-09-11
1
-4
/
+4
*
Backport r214946: [AArch64] One-liner: fix type of an add in SIMD registers
alalaw01
2014-09-11
1
-1
/
+1
*
Backport r214953 from mainline
alalaw01
2014-09-11
1
-246
/
+240
*
gcc/
gjl
2014-09-11
1
-6
/
+36
*
2014-09-10 Michael Meissner <meissner@linux.vnet.ibm.com>
meissner
2014-09-10
1
-11
/
+11
*
Backport r215136 from trunk
davidxl
2014-09-10
1
-2
/
+8
*
2014-09-09 Bill Schmidt <wschmidt@us.ibm.com>
wschmidt
2014-09-09
1
-1
/
+1
*
PR target/62040
carrot
2014-09-04
2
-4
/
+42
*
PR target/62261
kkojima
2014-09-02
1
-0
/
+36
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