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* unsupported insn for bswap emittedDoug Gilbert2017-10-061-1/+1
* Indicate that PPE42 fused branch instructions modify the CRDoug Gilbert2017-08-182-16/+27
* Prevent unsupported load/store index updateinstructions on PPEDoug Gilbert2017-02-101-5/+119
* Fix compile issue when compiling with gcc 6Douglas Gilbert2017-01-171-2/+2
* Fix insn attribute length field for load zero-extend operationDoug Gilbert2016-10-282-29/+22
* PPE42 compare immediate branch with immediate value out of rangeDoug Gilbert2016-09-131-4/+21
* requre 8 byte alignment on offsettable memory access for 64bit load/storeDoug Gilbert2016-08-153-6/+27
* Add RTL to correctly handle unavailable lwzux instructionDoug Gilbert2016-08-151-2/+15
* PPE42 compiler generates invalid crnot instructionDoug Gilbert2016-08-151-2/+6
* Turn off 64bit load/stores in epilog/proglogDoug Gilbert2016-08-152-4/+6
* Fix PPE42 illegal stwux asm commandDoug Gilbert2016-08-152-2/+26
* Unsigned compare immediate branch emitting wrong instructionsDoug Gilbert2016-08-152-1/+7
* Remove more places lbzux was being usedDoug Gilbert2016-08-151-466/+507
* Fix where signed compare should be unsigned compareDoug Gilbert2016-08-151-11/+10
* Delivered 05/2015Doug Gilbert2016-08-152-1/+3
* provide clrbwibcDoug Gilbert2016-08-152-30/+45
* bnbwi supportDoug Gilbert2016-08-154-6/+144
* Add ppe405 and ppe42 cpu typesDoug Gilbert2016-08-157-111/+144
* 64 bit load/store peepholesDoug Gilbert2016-08-153-13/+188
* 64 bit load/storeDoug Gilbert2016-08-153-19/+43
* Compare-branch fused instructionsDoug Gilbert2016-08-154-31/+204
* hack1Doug Gilbert2016-08-154-890/+900
* [AArch64] Restore recog state after finding pre-madd instructionktkachov2014-10-291-0/+4
* [gcc]wschmidt2014-10-133-5/+60
* [AArch64] Add --enable-fix-cortex-a53-835769 configure-time optionktkachov2014-10-102-1/+10
* [AArch64] Implement workaround for ARM Cortex-A53 erratum 835769ktkachov2014-10-104-0/+137
* gcc/olegendo2014-10-081-2/+12
* PR target/63428jakub2014-10-011-2/+2
* [PATCH][ARM] Disable store_minmaxsi pattern for arm_restrict_iktkachov2014-10-011-1/+1
* Backport from mainlineuros2014-10-011-6/+12
* PR target/61407fxcoudert2014-09-292-25/+35
* 2014-09-29 Charles Baylis <charles.baylis@linaro.org>cbaylis2014-09-294-23/+31
* * config/pa/pa.c (pa_output_function_epilogue): Only updatedanglin2014-09-281-3/+6
* gcc/olegendo2014-09-251-2/+2
* [gcc]wschmidt2014-09-251-1/+2
* 2014-09-23 Michael Meissner <meissner@linux.vnet.ibm.com>meissner2014-09-231-10/+27
* 2014-09-19 Michael Meissner <meissner@linux.vnet.ibm.com>meissner2014-09-194-109/+119
* 2014-09-19 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>krebbel2014-09-191-5/+14
* PR target/61853danglin2014-09-161-2/+8
* * config/msp430/msp430.md (extendhipsi2): Use 20-bit form of RLAM/RRAM.dj2014-09-121-3/+3
* Also turn off OPTION_MASK_ABI_X32 for -m16hjl2014-09-111-2/+3
* [AArch64] Cheap fix for argument types of vmull_high_lane_{us}{16,32}jgreenhalgh2014-09-111-4/+4
* Backport r214946: [AArch64] One-liner: fix type of an add in SIMD registersalalaw012014-09-111-1/+1
* Backport r214953 from mainlinealalaw012014-09-111-246/+240
* gcc/gjl2014-09-111-6/+36
* 2014-09-10 Michael Meissner <meissner@linux.vnet.ibm.com>meissner2014-09-101-11/+11
* Backport r215136 from trunkdavidxl2014-09-101-2/+8
* 2014-09-09 Bill Schmidt <wschmidt@us.ibm.com>wschmidt2014-09-091-1/+1
* PR target/62040carrot2014-09-042-4/+42
* PR target/62261kkojima2014-09-021-0/+36
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