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| author | davem <davem@138bc75d-0d04-0410-961f-82ee72b054a4> | 2011-11-01 08:42:57 +0000 |
|---|---|---|
| committer | davem <davem@138bc75d-0d04-0410-961f-82ee72b054a4> | 2011-11-01 08:42:57 +0000 |
| commit | efa273f5e98836fe1d9dd6be4200fd4d35db2bf5 (patch) | |
| tree | 4eb3d5949906628acafc358484369b9d60d0d499 /gcc/config/sparc/sparc.md | |
| parent | e8c738ce09f392714aaf0f19cd05a9369740b9d2 (diff) | |
| download | ppe42-gcc-efa273f5e98836fe1d9dd6be4200fd4d35db2bf5.tar.gz ppe42-gcc-efa273f5e98836fe1d9dd6be4200fd4d35db2bf5.zip | |
Add vcond/vcondu patterns to sparc backend.
* config/sparc/sparc.c (sparc_expand_vcond): New function.
* config/sparc/sparc-protos.h (sparc_expand_vcond): Declare it.
* config/sparc/sparc.md (vcond<mode><mode>): New VIS3 expander.
(vconduv8qiv8qi): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@180733 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/sparc/sparc.md')
| -rw-r--r-- | gcc/config/sparc/sparc.md | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index fbd1a871921..592440389e5 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -8299,6 +8299,36 @@ [(set_attr "type" "fpmul") (set_attr "fptype" "double")]) +(define_expand "vcond<mode><mode>" + [(match_operand:GCM 0 "register_operand" "") + (match_operand:GCM 1 "register_operand" "") + (match_operand:GCM 2 "register_operand" "") + (match_operator 3 "" + [(match_operand:GCM 4 "register_operand" "") + (match_operand:GCM 5 "register_operand" "")])] + "TARGET_VIS3" +{ + sparc_expand_vcond (<MODE>mode, operands, + UNSPEC_CMASK<gcm_name>, + UNSPEC_FCMP); + DONE; +}) + +(define_expand "vconduv8qiv8qi" + [(match_operand:V8QI 0 "register_operand" "") + (match_operand:V8QI 1 "register_operand" "") + (match_operand:V8QI 2 "register_operand" "") + (match_operator 3 "" + [(match_operand:V8QI 4 "register_operand" "") + (match_operand:V8QI 5 "register_operand" "")])] + "TARGET_VIS3" +{ + sparc_expand_vcond (V8QImode, operands, + UNSPEC_CMASK8, + UNSPEC_FUCMP); + DONE; +}) + (define_insn "array8<P:mode>_vis" [(set (match_operand:P 0 "register_operand" "=r") (unspec:P [(match_operand:P 1 "register_or_zero_operand" "rJ") |
