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path: root/llvm/utils/TableGen/X86RecognizableInstr.cpp
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* X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by ↵Craig Topper2012-02-271-0/+5
| | | | | | Kay Tiong Khoo. llvm-svn: 151510
* Add vmfunc instruction to X86 assembler and disassembler.Craig Topper2012-02-191-8/+9
| | | | llvm-svn: 150899
* Add X86 assembler and disassembler support for AMD SVM instructions. ↵Craig Topper2012-02-181-1/+9
| | | | | | Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication. llvm-svn: 150873
* Add disassembler support for VPERMIL2PD and VPERMIL2PS.Craig Topper2011-12-301-5/+9
| | | | llvm-svn: 147368
* Add FMA4 instructions to disassembler.Craig Topper2011-12-301-0/+7
| | | | llvm-svn: 147367
* Remove some unnecessary filtering checks from X86 disassembler table build.Craig Topper2011-11-191-35/+8
| | | | llvm-svn: 144986
* More AVX2 instructions and their intrinsics.Craig Topper2011-11-061-3/+6
| | | | llvm-svn: 143895
* Add X86 RORX instructionCraig Topper2011-10-231-14/+23
| | | | llvm-svn: 142741
* Add X86 PEXTR and PDEP instructions.Craig Topper2011-10-161-18/+27
| | | | llvm-svn: 142141
* Add X86 BZHI instruction as well as BMI2 feature detection.Craig Topper2011-10-161-13/+9
| | | | llvm-svn: 142122
* Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, ↵Craig Topper2011-10-161-4/+0
| | | | | | VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. llvm-svn: 142117
* Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand ↵Craig Topper2011-10-161-5/+18
| | | | | | 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen llvm-svn: 142105
* Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work ↵Craig Topper2011-10-151-8/+50
| | | | | | because these are the first VEX encoded instructions to use the reg field as an opcode extension. llvm-svn: 142082
* Add X86 ANDN instruction. Including instruction selection.Craig Topper2011-10-141-0/+2
| | | | llvm-svn: 141947
* Fix disassembling of popcntw. Also remove some code that says it accounts ↵Craig Topper2011-10-111-2/+8
| | | | | | for 64BIT_REXW_XD not existing, but it does exist. llvm-svn: 141642
* Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This ↵Craig Topper2011-10-061-0/+6
| | | | | | was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. llvm-svn: 141274
* Add support in the disassembler for ignoring the L-bit on certain VEX ↵Craig Topper2011-10-041-4/+7
| | | | | | instructions. Mark instructions that have this behavior. Fixes PR10676. llvm-svn: 141065
* Fix disassembling of INVEPT and INVVPID to take operandsCraig Topper2011-10-011-0/+2
| | | | llvm-svn: 140955
* Fix disassembler handling of CRC32 which is an odd instruction that uses ↵Craig Topper2011-10-011-6/+9
| | | | | | 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. llvm-svn: 140954
* Don't allow 32-bit only instructions to be disassembled in 64-bit mode. ↵Craig Topper2011-09-231-3/+8
| | | | | | Fixes part of PR10700. llvm-svn: 140370
* Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND ↵Craig Topper2011-09-141-5/+0
| | | | | | from being recognized by disassembler. llvm-svn: 139691
* Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from ↵Craig Topper2011-09-131-3/+1
| | | | | | being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. llvm-svn: 139588
* Fix disassembling of reverse register/register forms of ↵Craig Topper2011-09-111-1/+1
| | | | | | ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV. llvm-svn: 139485
* Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP ↵Craig Topper2011-09-111-1/+2
| | | | | | disassembling to ignore OpSize and REX.W. llvm-svn: 139484
* Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702.Kevin Enderby2011-09-021-2/+5
| | | | llvm-svn: 139014
* Add vvvv support to disassembling of instructions with MRMDestMem and ↵Craig Topper2011-08-301-4/+27
| | | | | | MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807. llvm-svn: 138795
* Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217Kevin Enderby2011-08-291-2/+3
| | | | llvm-svn: 138771
* Unconstify InitsDavid Greene2011-07-291-3/+3
| | | | | | Remove const qualifiers from Init references, per Chris' request. llvm-svn: 136531
* [AVX] Constify InitsDavid Greene2011-07-291-3/+3
| | | | | | | Make references to Inits const everywhere. This is the final step before making them unique. llvm-svn: 136485
* Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.Kevin Enderby2011-07-271-0/+2
| | | | | | | | | | | | llvm-mc gives an "invalid operand" error for instructions that take an unsigned immediate which have the high bit set such as: pblendw $0xc5, %xmm2, %xmm1 llvm-mc treats all x86 immediates as signed values and range checks them. A small number of x86 instructions use the imm8 field as a set of bits. This change only changes those instructions and where the high bit is not ignored. The others remain unchanged. llvm-svn: 136287
* Make the disassembler able to disassemble a bunch of instructions with names ↵Eli Friedman2011-07-161-1/+25
| | | | | | in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873. llvm-svn: 135337
* Revert r134921, 134917, 134908 and 134907. They're causing failuresEric Christopher2011-07-111-3/+3
| | | | | | in multiple buildbots. llvm-svn: 134936
* [AVX] Make Inits FoldableDavid Greene2011-07-111-3/+3
| | | | | | | | | | | | | | | | | | Manage Inits in a FoldingSet. This provides several benefits: - Memory for Inits is properly managed - Duplicate Inits are folded into Flyweights, saving memory - It enforces const-correctness, protecting against certain classes of bugs The above benefits allow Inits to be used in more contexts, which in turn provides more dynamism to TableGen. This enhanced capability will be used by the AVX code generator to a fold common patterns together. llvm-svn: 134907
* Add support for the VIA PadLock instructions.Joerg Sonnenberger2011-04-041-1/+17
| | | | llvm-svn: 128826
* X86 table-generator and disassembler support for the AVXSean Callanan2011-03-151-48/+177
| | | | | | | | | instruction set. This code adds support for the VEX prefix and for the YMM registers accessible on AVX-enabled architectures. Instruction table support that enables AVX instructions for the disassembler is in an upcoming patch. llvm-svn: 127644
* Implement xgetbv and xsetbv.Rafael Espindola2011-02-221-1/+3
| | | | | | Patch by Jai Menon. llvm-svn: 126165
* In Thumb2, direct branches can be encoded as either a "short" conditional ↵Owen Anderson2010-12-131-0/+1
| | | | | | | | | | branch with a null predicate, or as a "long" direct branch. While the mnemonics are the same, they encode the branch offset differently, and the Darwin assembler appears to prefer the "long" form for direct branches. Thus, in the name of bitwise equivalence, provide encoding and fixup support for it. llvm-svn: 121710
* factor the operand list (and related fields/operations) out of Chris Lattner2010-11-011-3/+3
| | | | | | CodeGenInstruction into its own helper class. No functionality change. llvm-svn: 117893
* Added the x86 instruction ud2b (2nd official undefined instruction).Kevin Enderby2010-10-271-1/+0
| | | | llvm-svn: 117485
* Fixed the disassembler to handle two new X86Sean Callanan2010-10-041-1/+16
| | | | | | | instruction forms. Now the ENTER instruction disassembles correctly. llvm-svn: 115573
* Massive rewrite of MMX: Dale Johannesen2010-09-301-6/+0
| | | | | | | | | | | | | | | | | | | The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. llvm-svn: 115243
* add basic avx support to the disassembler, also teach it about ssmem/sdmemChris Lattner2010-09-291-0/+6
| | | | | | | | | | operands. With this done, we can remove the _Int suffixes from the round instructions without the disassembler blowing up. This allows the assembler to support them, implementing rdar://8456376 - llvm-mc rejects 'roundss' llvm-svn: 115019
* Add patterns for MMX that use the new intrinsics.Dale Johannesen2010-09-071-1/+7
| | | | | | | Enable palignr intrinsic. These may need adjustment for a new VT in due course. llvm-svn: 113233
* Convert some tab stops into spaces.Duncan Sands2010-07-121-1/+1
| | | | llvm-svn: 108130
* Implement the major chunk of PR7195: support for 'callw'Chris Lattner2010-07-071-0/+2
| | | | | | | in the integrated assembler. Still some discussion to be done. llvm-svn: 107825
* More AVX instructions ({ADD,SUB,MUL,DIV}{SS,SD}rm)Bruno Cardoso Lopes2010-06-111-1/+8
| | | | | | Introduce the VEX_X field llvm-svn: 105859
* Reapply r105521, this time appending "LLU" to 64 bitBruno Cardoso Lopes2010-06-081-1/+7
| | | | | | immediates to avoid breaking the build. llvm-svn: 105652
* revert r105521, which is breaking the buildbots with stuff like this:Chris Lattner2010-06-051-7/+1
| | | | | | | | | | | | | | In file included from X86InstrInfo.cpp:16: X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type llvm-svn: 105524
* Initial AVX support for some instructions. No patterns matchedBruno Cardoso Lopes2010-06-051-1/+7
| | | | | | yet, only assembly encoding support. llvm-svn: 105521
* tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honorDaniel Dunbar2010-05-201-0/+4
| | | | | | it. llvm-svn: 104270
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